From: Yu Chien Peter Lin <peterlin@andestech.com> To: <acme@kernel.org>, <adrian.hunter@intel.com>, <ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>, <andre.przywara@arm.com>, <anup@brainfault.org>, <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>, <conor+dt@kernel.org>, <conor.dooley@microchip.com>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <dminus@andestech.com>, <evan@rivosinc.com>, <geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>, <irogers@google.com>, <jernej.skrabec@gmail.com>, <jolsa@kernel.org>, <jszhang@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>, <linux-renesas-soc@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>, <locus84@andestech.com>, <magnus.damm@gmail.com>, <mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>, <namhyung@kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <peterlin@andestech.com>, <peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <sunilvl@ventanamicro.com>, <tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>, <inochiama@outlook.com> Subject: [PATCH v5 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Date: Wed, 13 Dec 2023 15:02:47 +0800 [thread overview] Message-ID: <20231213070301.1684751-3-peterlin@andestech.com> (raw) In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> Currently, the implementation of the RISC-V INTC driver uses the interrupt cause as hardware interrupt number and has a limitation of supporting a maximum of 64 interrupts. However, according to the privileged spec, interrupt causes >= 16 are defined for platform use. This limitation prevents to fully utilize the available local interrupt sources. Additionally, the interrupt number used on RISC-V are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf or T-Head's PMU interrupt) being currently used for supervisor mode. Switch to using irq_domain_create_tree() to create the radix tree map, so a larger number of hardware interrupts can be handled. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> --- Changes v1 -> v2: - Fixed irq mapping failure checking (suggested by Clément and Anup) Changes v2 -> v3: - No change Changes v3 -> v4: (Suggested by Thomas [1]) - Use pr_warn_ratelimited instead - Fix coding style and commit message Changes v4 -> v5: (Suggested by Thomas) - Fix commit message [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085 --- drivers/irqchip/irq-riscv-intc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..2fdd40f2a791 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -24,10 +24,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; - if (unlikely(cause >= BITS_PER_LONG)) - panic("unexpected interrupt cause"); - - generic_handle_domain_irq(intc_domain, cause); + if (generic_handle_domain_irq(intc_domain, cause)) + pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", + cause); } /* @@ -117,8 +116,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) { int rc; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); - return 0; } -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Yu Chien Peter Lin <peterlin@andestech.com> To: <acme@kernel.org>, <adrian.hunter@intel.com>, <ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>, <andre.przywara@arm.com>, <anup@brainfault.org>, <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>, <conor+dt@kernel.org>, <conor.dooley@microchip.com>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <dminus@andestech.com>, <evan@rivosinc.com>, <geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>, <irogers@google.com>, <jernej.skrabec@gmail.com>, <jolsa@kernel.org>, <jszhang@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>, <linux-renesas-soc@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>, <locus84@andestech.com>, <magnus.damm@gmail.com>, <mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>, <namhyung@kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <peterlin@andestech.com>, <peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <sunilvl@ventanamicro.com>, <tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>, <inochiama@outlook.com> Subject: [PATCH v5 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Date: Wed, 13 Dec 2023 15:02:47 +0800 [thread overview] Message-ID: <20231213070301.1684751-3-peterlin@andestech.com> (raw) In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> Currently, the implementation of the RISC-V INTC driver uses the interrupt cause as hardware interrupt number and has a limitation of supporting a maximum of 64 interrupts. However, according to the privileged spec, interrupt causes >= 16 are defined for platform use. This limitation prevents to fully utilize the available local interrupt sources. Additionally, the interrupt number used on RISC-V are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf or T-Head's PMU interrupt) being currently used for supervisor mode. Switch to using irq_domain_create_tree() to create the radix tree map, so a larger number of hardware interrupts can be handled. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> --- Changes v1 -> v2: - Fixed irq mapping failure checking (suggested by Clément and Anup) Changes v2 -> v3: - No change Changes v3 -> v4: (Suggested by Thomas [1]) - Use pr_warn_ratelimited instead - Fix coding style and commit message Changes v4 -> v5: (Suggested by Thomas) - Fix commit message [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085 --- drivers/irqchip/irq-riscv-intc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..2fdd40f2a791 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -24,10 +24,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; - if (unlikely(cause >= BITS_PER_LONG)) - panic("unexpected interrupt cause"); - - generic_handle_domain_irq(intc_domain, cause); + if (generic_handle_domain_irq(intc_domain, cause)) + pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", + cause); } /* @@ -117,8 +116,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) { int rc; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); - return 0; } -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-12-13 7:04 UTC|newest] Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-12-13 7:02 [PATCH v5 00/16] Support Andes PMU extension Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin [this message] 2023-12-13 7:02 ` [PATCH v5 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin 2023-12-13 14:28 ` Anup Patel 2023-12-13 14:28 ` Anup Patel 2023-12-13 15:19 ` Anup Patel 2023-12-13 15:19 ` Anup Patel 2023-12-19 7:43 ` Yu-Chien Peter Lin 2023-12-19 7:43 ` Yu-Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 14:45 ` Anup Patel 2023-12-13 14:45 ` Anup Patel 2023-12-13 15:44 ` Yu-Chien Peter Lin 2023-12-13 15:44 ` Yu-Chien Peter Lin 2023-12-13 15:48 ` Anup Patel 2023-12-13 15:48 ` Anup Patel 2023-12-13 7:02 ` [PATCH v5 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 15:27 ` Conor Dooley 2023-12-13 15:27 ` Conor Dooley 2023-12-13 15:27 ` Conor Dooley 2023-12-13 15:32 ` Conor Dooley 2023-12-13 15:32 ` Conor Dooley 2023-12-13 15:32 ` Conor Dooley 2023-12-13 7:02 ` [PATCH v5 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 15:26 ` Conor Dooley 2023-12-13 15:26 ` Conor Dooley 2023-12-13 15:26 ` Conor Dooley 2023-12-13 7:02 ` [PATCH v5 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 7:02 ` [PATCH v5 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 15:23 ` Conor Dooley 2023-12-13 15:23 ` Conor Dooley 2023-12-13 15:23 ` Conor Dooley 2023-12-13 7:02 ` [PATCH v5 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 15:24 ` Conor Dooley 2023-12-13 15:24 ` Conor Dooley 2023-12-13 15:24 ` Conor Dooley 2023-12-13 7:02 ` [PATCH v5 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin 2023-12-13 7:02 ` Yu Chien Peter Lin 2023-12-13 15:23 ` Conor Dooley 2023-12-13 15:23 ` Conor Dooley 2023-12-13 15:23 ` Conor Dooley 2023-12-13 7:03 ` [PATCH v5 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin 2023-12-13 7:03 ` Yu Chien Peter Lin 2023-12-13 15:24 ` Conor Dooley 2023-12-13 15:24 ` Conor Dooley 2023-12-13 15:24 ` Conor Dooley 2023-12-13 7:03 ` [PATCH v5 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin 2023-12-13 7:03 ` Yu Chien Peter Lin
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