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From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-pwm@vger.kernel.org>
Cc: "Emil Renner Berthing" <kernel@esmil.dk>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Hal Feng" <hal.feng@starfivetech.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"William Qiu" <william.qiu@starfivetech.com>
Subject: [PATCH v10 4/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration
Date: Fri, 22 Dec 2023 17:45:48 +0800	[thread overview]
Message-ID: <20231222094548.54103-5-william.qiu@starfivetech.com> (raw)
In-Reply-To: <20231222094548.54103-1-william.qiu@starfivetech.com>

Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2.dtsi         | 22 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  9 ++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index b89e9791efa7..e08af8a830ab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -323,6 +323,12 @@ reserved-data@600000 {
 	};
 };
 
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
 &spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_pins>;
@@ -513,6 +519,22 @@ GPOEN_ENABLE,
 		};
 	};
 
+	pwm_pins: pwm-0 {
+		pwm-pins {
+			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+					      GPOEN_SYS_PWM0_CHANNEL0,
+					      GPI_NONE)>,
+				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+					      GPOEN_SYS_PWM0_CHANNEL1,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
 	spi0_pins: spi0-0 {
 		mosi-pins {
 			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 45213cdf50dc..1b782f2c1395 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -829,6 +829,15 @@ i2stx1: i2s@120c0000 {
 			status = "disabled";
 		};
 
+		pwm: pwm@120d0000 {
+			compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
+			reg = <0x0 0x120d0000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
+			resets = <&syscrg JH7110_SYSRST_PWM_APB>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		sfctemp: temperature-sensor@120e0000 {
 			compatible = "starfive,jh7110-temp";
 			reg = <0x0 0x120e0000 0x0 0x10000>;
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-pwm@vger.kernel.org>
Cc: "Emil Renner Berthing" <kernel@esmil.dk>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Hal Feng" <hal.feng@starfivetech.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"William Qiu" <william.qiu@starfivetech.com>
Subject: [PATCH v10 4/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration
Date: Fri, 22 Dec 2023 17:45:48 +0800	[thread overview]
Message-ID: <20231222094548.54103-5-william.qiu@starfivetech.com> (raw)
In-Reply-To: <20231222094548.54103-1-william.qiu@starfivetech.com>

Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2.dtsi         | 22 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  9 ++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index b89e9791efa7..e08af8a830ab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -323,6 +323,12 @@ reserved-data@600000 {
 	};
 };
 
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
 &spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_pins>;
@@ -513,6 +519,22 @@ GPOEN_ENABLE,
 		};
 	};
 
+	pwm_pins: pwm-0 {
+		pwm-pins {
+			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+					      GPOEN_SYS_PWM0_CHANNEL0,
+					      GPI_NONE)>,
+				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+					      GPOEN_SYS_PWM0_CHANNEL1,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
 	spi0_pins: spi0-0 {
 		mosi-pins {
 			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 45213cdf50dc..1b782f2c1395 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -829,6 +829,15 @@ i2stx1: i2s@120c0000 {
 			status = "disabled";
 		};
 
+		pwm: pwm@120d0000 {
+			compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
+			reg = <0x0 0x120d0000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
+			resets = <&syscrg JH7110_SYSRST_PWM_APB>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		sfctemp: temperature-sensor@120e0000 {
 			compatible = "starfive,jh7110-temp";
 			reg = <0x0 0x120e0000 0x0 0x10000>;
-- 
2.34.1


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  parent reply	other threads:[~2023-12-22  9:45 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-22  9:45 [PATCH v10 0/4] StarFive's Pulse Width Modulation driver support William Qiu
2023-12-22  9:45 ` William Qiu
2023-12-22  9:45 ` [PATCH v10 1/4] dt-bindings: pwm: Add bindings for OpenCores PWM Controller William Qiu
2023-12-22  9:45   ` William Qiu
2024-01-04 22:43   ` Uwe Kleine-König
2024-01-04 22:43     ` Uwe Kleine-König
2024-01-08 21:03     ` Uwe Kleine-König
2024-01-08 21:03       ` Uwe Kleine-König
2024-01-09 17:15       ` Conor Dooley
2024-01-09 17:15         ` Conor Dooley
2023-12-22  9:45 ` [PATCH v10 2/4] pwm: opencores: Add PWM driver support William Qiu
2023-12-22  9:45   ` William Qiu
2024-01-03  7:15   ` William Qiu
2024-01-03  7:15     ` William Qiu
2024-01-03 12:22     ` Uwe Kleine-König
2024-01-03 12:22       ` Uwe Kleine-König
2024-01-04 22:40   ` Uwe Kleine-König
2024-01-04 22:40     ` Uwe Kleine-König
2024-01-05  8:02     ` William Qiu
2024-01-05  8:02       ` William Qiu
2023-12-22  9:45 ` [PATCH v10 3/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration William Qiu
2023-12-22  9:45   ` William Qiu
2023-12-24 10:49   ` Emil Renner Berthing
2023-12-24 10:49     ` Emil Renner Berthing
2024-01-04 22:46     ` Uwe Kleine-König
2024-01-04 22:46       ` Uwe Kleine-König
2024-01-05 13:18       ` Emil Renner Berthing
2024-01-05 13:18         ` Emil Renner Berthing
2024-01-08 17:31         ` Conor Dooley
2024-01-08 17:31           ` Conor Dooley
2023-12-22  9:45 ` William Qiu [this message]
2023-12-22  9:45   ` [PATCH v10 4/4] riscv: dts: starfive: jh7110: " William Qiu
2023-12-24 10:50   ` Emil Renner Berthing
2023-12-24 10:50     ` Emil Renner Berthing
2024-01-22 16:50 ` (subset) [PATCH v10 0/4] StarFive's Pulse Width Modulation driver support Conor Dooley
2024-01-22 16:55   ` Conor Dooley
2024-01-22 16:55     ` Conor Dooley

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