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From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
	<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>, <chao.wei@sophgo.com>,
	<unicorn_wang@outlook.com>, <wefu@redhat.com>
Cc: Randolph <randolph@andestech.com>
Subject: [PATCH v6 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Mon, 25 Dec 2023 18:32:54 +0800	[thread overview]
Message-ID: <20231225103308.1557548-3-peterlin@andestech.com> (raw)
In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com>

Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.

To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
---
Changes v1 -> v2:
  - Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
  - No change
Changes v3 -> v4: (Suggested by Thomas [1])
  - Use pr_warn_ratelimited instead
  - Fix coding style and commit message
Changes v4 -> v5: (Suggested by Thomas)
  - Fix commit message
Changes v5 -> v6: (Suggested by Anup [2])
  - Add riscv_intc_* global variables for checking range in riscv_intc_domain_alloc()
  - Advertise the number of interrupts allowed

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
[2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
---
 drivers/irqchip/irq-riscv-intc.c | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..e1d80cb0020e 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,17 @@
 #include <linux/smp.h>
 
 static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init;
+static unsigned int riscv_intc_custom_base __ro_after_init;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
 
 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
 
-	if (unlikely(cause >= BITS_PER_LONG))
-		panic("unexpected interrupt cause");
-
-	generic_handle_domain_irq(intc_domain, cause);
+	if (generic_handle_domain_irq(intc_domain, cause))
+		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
+				    cause);
 }
 
 /*
@@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
 	if (ret)
 		return ret;
 
+	/*
+	 * Only allow hwirq for which we have corresponding standard or
+	 * custom interrupt enable register.
+	 */
+	if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
+	    (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
+		return -EINVAL;
+
 	for (i = 0; i < nr_irqs; i++) {
 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
 		if (ret)
@@ -117,8 +127,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
-					       &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -132,7 +141,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 
 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+	if (riscv_intc_custom_nr_irqs)
+		pr_info("%d (%d - %d) custom local interrupts mapped\n",
+			riscv_intc_custom_nr_irqs, riscv_intc_custom_base,
+			riscv_intc_custom_base + riscv_intc_custom_nr_irqs);
 
 	return 0;
 }
@@ -166,6 +179,10 @@ static int __init riscv_intc_init(struct device_node *node,
 		return 0;
 	}
 
+	riscv_intc_nr_irqs = BITS_PER_LONG;
+	riscv_intc_custom_base = riscv_intc_nr_irqs;
+	riscv_intc_custom_nr_irqs = 0;
+
 	return riscv_intc_init_common(of_node_to_fwnode(node));
 }
 
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
	<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>, <chao.wei@sophgo.com>,
	<unicorn_wang@outlook.com>, <wefu@redhat.com>
Cc: Randolph <randolph@andestech.com>
Subject: [PATCH v6 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Mon, 25 Dec 2023 18:32:54 +0800	[thread overview]
Message-ID: <20231225103308.1557548-3-peterlin@andestech.com> (raw)
In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com>

Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.

To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
---
Changes v1 -> v2:
  - Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
  - No change
Changes v3 -> v4: (Suggested by Thomas [1])
  - Use pr_warn_ratelimited instead
  - Fix coding style and commit message
Changes v4 -> v5: (Suggested by Thomas)
  - Fix commit message
Changes v5 -> v6: (Suggested by Anup [2])
  - Add riscv_intc_* global variables for checking range in riscv_intc_domain_alloc()
  - Advertise the number of interrupts allowed

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
[2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
---
 drivers/irqchip/irq-riscv-intc.c | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..e1d80cb0020e 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,17 @@
 #include <linux/smp.h>
 
 static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init;
+static unsigned int riscv_intc_custom_base __ro_after_init;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
 
 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
 
-	if (unlikely(cause >= BITS_PER_LONG))
-		panic("unexpected interrupt cause");
-
-	generic_handle_domain_irq(intc_domain, cause);
+	if (generic_handle_domain_irq(intc_domain, cause))
+		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
+				    cause);
 }
 
 /*
@@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
 	if (ret)
 		return ret;
 
+	/*
+	 * Only allow hwirq for which we have corresponding standard or
+	 * custom interrupt enable register.
+	 */
+	if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
+	    (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
+		return -EINVAL;
+
 	for (i = 0; i < nr_irqs; i++) {
 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
 		if (ret)
@@ -117,8 +127,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
-					       &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -132,7 +141,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 
 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+	if (riscv_intc_custom_nr_irqs)
+		pr_info("%d (%d - %d) custom local interrupts mapped\n",
+			riscv_intc_custom_nr_irqs, riscv_intc_custom_base,
+			riscv_intc_custom_base + riscv_intc_custom_nr_irqs);
 
 	return 0;
 }
@@ -166,6 +179,10 @@ static int __init riscv_intc_init(struct device_node *node,
 		return 0;
 	}
 
+	riscv_intc_nr_irqs = BITS_PER_LONG;
+	riscv_intc_custom_base = riscv_intc_nr_irqs;
+	riscv_intc_custom_nr_irqs = 0;
+
 	return riscv_intc_init_common(of_node_to_fwnode(node));
 }
 
-- 
2.34.1


  parent reply	other threads:[~2023-12-25 10:35 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-25 10:32 [PATCH v6 00/16] Support Andes PMU extension Yu Chien Peter Lin
2023-12-25 10:32 ` Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-12-25 10:32   ` Yu Chien Peter Lin
2023-12-25 10:32 ` Yu Chien Peter Lin [this message]
2023-12-25 10:32   ` [PATCH v6 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-25 10:32   ` Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-12-25 10:32   ` Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-12-25 10:32   ` Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-12-25 10:32   ` Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-12-25 10:32   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2023-12-25 10:33   ` Yu Chien Peter Lin
2023-12-25 21:06 ` [PATCH v6 00/16] Support Andes PMU extension Lad, Prabhakar
2023-12-25 21:06   ` Lad, Prabhakar
2023-12-26  2:59   ` Yu-Chien Peter Lin
2023-12-26  2:59     ` Yu-Chien Peter Lin

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