From: Eric Biggers <ebiggers@kernel.org> To: linux-crypto@vger.kernel.org, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, "Albert Ou" <aou@eecs.berkeley.edu>, "Andy Chiu" <andy.chiu@sifive.com>, "Ard Biesheuvel" <ardb@kernel.org>, "Christoph Müllner" <christoph.muellner@vrull.eu>, "Heiko Stuebner" <heiko@sntech.de>, "Jerry Shih" <jerry.shih@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Phoebe Chen" <phoebe.chen@sifive.com>, hongrong.hsu@sifive.com, "Heiko Stuebner" <heiko.stuebner@vrull.eu> Subject: [PATCH v3 01/10] RISC-V: add helper function to read the vector VLEN Date: Sun, 21 Jan 2024 16:19:12 -0800 [thread overview] Message-ID: <20240122002024.27477-2-ebiggers@kernel.org> (raw) In-Reply-To: <20240122002024.27477-1-ebiggers@kernel.org> From: Heiko Stuebner <heiko.stuebner@vrull.eu> VLEN describes the length of each vector register and some instructions need specific minimal VLENs to work correctly. The vector code already includes a variable riscv_v_vsize that contains the value of "32 vector registers with vlenb length" that gets filled during boot. vlenb is the value contained in the CSR_VLENB register and the value represents "VLEN / 8". So add riscv_vector_vlen() to return the actual VLEN value for in-kernel users when they need to check the available VLEN. Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Eric Biggers <ebiggers@google.com> --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 0cd6f0a027d1f..731dcd0ed4de9 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -277,11 +277,22 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define riscv_v_vstate_restore(vstate, regs) do {} while (0) #define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) #define riscv_v_thread_free(tsk) do {} while (0) #define riscv_v_setup_ctx_cache() do {} while (0) #define riscv_v_thread_alloc(tsk) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ +/* + * Return the implementation's vlen value. + * + * riscv_v_vsize contains the value of "32 vector registers with vlenb length" + * so rebuild the vlen value in bits from it. + */ +static inline int riscv_vector_vlen(void) +{ + return riscv_v_vsize / 32 * 8; +} + #endif /* ! __ASM_RISCV_VECTOR_H */ -- 2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Eric Biggers <ebiggers@kernel.org> To: linux-crypto@vger.kernel.org, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, "Albert Ou" <aou@eecs.berkeley.edu>, "Andy Chiu" <andy.chiu@sifive.com>, "Ard Biesheuvel" <ardb@kernel.org>, "Christoph Müllner" <christoph.muellner@vrull.eu>, "Heiko Stuebner" <heiko@sntech.de>, "Jerry Shih" <jerry.shih@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Phoebe Chen" <phoebe.chen@sifive.com>, hongrong.hsu@sifive.com, "Heiko Stuebner" <heiko.stuebner@vrull.eu> Subject: [PATCH v3 01/10] RISC-V: add helper function to read the vector VLEN Date: Sun, 21 Jan 2024 16:19:12 -0800 [thread overview] Message-ID: <20240122002024.27477-2-ebiggers@kernel.org> (raw) In-Reply-To: <20240122002024.27477-1-ebiggers@kernel.org> From: Heiko Stuebner <heiko.stuebner@vrull.eu> VLEN describes the length of each vector register and some instructions need specific minimal VLENs to work correctly. The vector code already includes a variable riscv_v_vsize that contains the value of "32 vector registers with vlenb length" that gets filled during boot. vlenb is the value contained in the CSR_VLENB register and the value represents "VLEN / 8". So add riscv_vector_vlen() to return the actual VLEN value for in-kernel users when they need to check the available VLEN. Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Eric Biggers <ebiggers@google.com> --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 0cd6f0a027d1f..731dcd0ed4de9 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -277,11 +277,22 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define riscv_v_vstate_restore(vstate, regs) do {} while (0) #define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) #define riscv_v_thread_free(tsk) do {} while (0) #define riscv_v_setup_ctx_cache() do {} while (0) #define riscv_v_thread_alloc(tsk) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ +/* + * Return the implementation's vlen value. + * + * riscv_v_vsize contains the value of "32 vector registers with vlenb length" + * so rebuild the vlen value in bits from it. + */ +static inline int riscv_vector_vlen(void) +{ + return riscv_v_vsize / 32 * 8; +} + #endif /* ! __ASM_RISCV_VECTOR_H */ -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-01-22 0:22 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-22 0:19 [PATCH v3 00/10] RISC-V crypto with reworked asm files Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` Eric Biggers [this message] 2024-01-22 0:19 ` [PATCH v3 01/10] RISC-V: add helper function to read the vector VLEN Eric Biggers 2024-01-22 0:19 ` [PATCH v3 02/10] RISC-V: add TOOLCHAIN_HAS_VECTOR_CRYPTO Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 03/10] RISC-V: hook new crypto subdir into build-system Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 04/10] crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS} Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 05/10] crypto: riscv - add vector crypto accelerated ChaCha20 Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-04-12 7:59 ` Yangyu Chen 2024-04-12 7:59 ` Yangyu Chen 2024-04-12 8:07 ` Jerry Shih 2024-04-12 8:07 ` Jerry Shih 2024-01-22 0:19 ` [PATCH v3 06/10] crypto: riscv - add vector crypto accelerated GHASH Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 07/10] crypto: riscv - add vector crypto accelerated SHA-{256,224} Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 08/10] crypto: riscv - add vector crypto accelerated SHA-{512,384} Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 09/10] crypto: riscv - add vector crypto accelerated SM3 Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-22 0:19 ` [PATCH v3 10/10] crypto: riscv - add vector crypto accelerated SM4 Eric Biggers 2024-01-22 0:19 ` Eric Biggers 2024-01-23 1:58 ` [PATCH v3 00/10] RISC-V crypto with reworked asm files Palmer Dabbelt 2024-01-23 1:58 ` Palmer Dabbelt 2024-01-23 15:06 ` Christoph Müllner 2024-01-23 15:06 ` Christoph Müllner 2024-01-23 17:50 ` patchwork-bot+linux-riscv 2024-01-23 17:50 ` patchwork-bot+linux-riscv
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