From: Tudor Ambarus <tudor.ambarus@linaro.org> To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus <tudor.ambarus@linaro.org> Subject: [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX, TX}_FIFO_LVL Date: Thu, 25 Jan 2024 14:49:48 +0000 [thread overview] Message-ID: <20240125145007.748295-11-tudor.ambarus@linaro.org> (raw) In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> SPI_STATUSn.{RX, TX}_FIFO_LVL fields show the data level in the RX and TX FIFOs. The IP supports FIFOs from 8 to 256 bytes, but apart from the MODE_CFG.{RX, TX}_RDY_LVL fields that configure the {RX, TX} FIFO trigger level in the interrupt mode, there's nothing in the registers that configure the FIFOs depth. Is the responsibility of the SoC that integrates the IP to dictate the FIFO depth and of the SPI driver to make sure it doesn't bypass the FIFO length. {RX, TX}_FIFO_LVL was used to pass the FIFO length information based on the IP configuration in the SoC. Its value was defined so that it includes the entire FIFO length. For example, if one wanted to specify a 64 FIFO length (0x40), it wold configure the FIFO level to 127 (0x7f). This is not only wrong, because it doesn't respect the IP's register fields, it's also misleading. Use the full mask for the SPI_STATUSn.{RX, TX}_FIFO_LVL fields. No change in functionality is expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d046810da51f..b048e81e6207 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -78,6 +78,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) +#define S3C64XX_SPI_ST_RX_FIFO_LVL GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_LVL GENMASK(14, 6) #define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) @@ -108,9 +110,6 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_POLLING_SIZE 32 @@ -219,7 +218,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - } while (TX_FIFO_LVL(val, sdd) && loops--); + } while (FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, val) && loops--); if (loops == 0) dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); @@ -228,7 +227,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(val, sdd)) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, val)) readl(regs + S3C64XX_SPI_RX_DATA); else break; @@ -499,10 +498,11 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < max_fifo && + --val); /* return the actual received data length */ - return RX_FIFO_LVL(status, sdd); + return FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); } static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, @@ -533,7 +533,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, if (val && !xfer->rx_buf) { val = msecs_to_loops(10); status = readl(regs + S3C64XX_SPI_STATUS); - while ((TX_FIFO_LVL(status, sdd) + while ((FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, status) || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) && --val) { cpu_relax(); @@ -568,7 +568,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, /* sleep during signal transfer time */ status = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(status, sdd) < xfer->len) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len) usleep_range(time_us / 2, time_us); if (use_irq) { @@ -580,7 +580,8 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, val = msecs_to_loops(ms); do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len && + --val); if (!val) return -EIO; -- 2.43.0.429.g432eaa2c6b-goog
WARNING: multiple messages have this Message-ID (diff)
From: Tudor Ambarus <tudor.ambarus@linaro.org> To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus <tudor.ambarus@linaro.org> Subject: [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX, TX}_FIFO_LVL Date: Thu, 25 Jan 2024 14:49:48 +0000 [thread overview] Message-ID: <20240125145007.748295-11-tudor.ambarus@linaro.org> (raw) In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> SPI_STATUSn.{RX, TX}_FIFO_LVL fields show the data level in the RX and TX FIFOs. The IP supports FIFOs from 8 to 256 bytes, but apart from the MODE_CFG.{RX, TX}_RDY_LVL fields that configure the {RX, TX} FIFO trigger level in the interrupt mode, there's nothing in the registers that configure the FIFOs depth. Is the responsibility of the SoC that integrates the IP to dictate the FIFO depth and of the SPI driver to make sure it doesn't bypass the FIFO length. {RX, TX}_FIFO_LVL was used to pass the FIFO length information based on the IP configuration in the SoC. Its value was defined so that it includes the entire FIFO length. For example, if one wanted to specify a 64 FIFO length (0x40), it wold configure the FIFO level to 127 (0x7f). This is not only wrong, because it doesn't respect the IP's register fields, it's also misleading. Use the full mask for the SPI_STATUSn.{RX, TX}_FIFO_LVL fields. No change in functionality is expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d046810da51f..b048e81e6207 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -78,6 +78,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) +#define S3C64XX_SPI_ST_RX_FIFO_LVL GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_LVL GENMASK(14, 6) #define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) @@ -108,9 +110,6 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_POLLING_SIZE 32 @@ -219,7 +218,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - } while (TX_FIFO_LVL(val, sdd) && loops--); + } while (FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, val) && loops--); if (loops == 0) dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); @@ -228,7 +227,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(val, sdd)) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, val)) readl(regs + S3C64XX_SPI_RX_DATA); else break; @@ -499,10 +498,11 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < max_fifo && + --val); /* return the actual received data length */ - return RX_FIFO_LVL(status, sdd); + return FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); } static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, @@ -533,7 +533,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, if (val && !xfer->rx_buf) { val = msecs_to_loops(10); status = readl(regs + S3C64XX_SPI_STATUS); - while ((TX_FIFO_LVL(status, sdd) + while ((FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, status) || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) && --val) { cpu_relax(); @@ -568,7 +568,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, /* sleep during signal transfer time */ status = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(status, sdd) < xfer->len) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len) usleep_range(time_us / 2, time_us); if (use_irq) { @@ -580,7 +580,8 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, val = msecs_to_loops(ms); do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len && + --val); if (!val) return -EIO; -- 2.43.0.429.g432eaa2c6b-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-25 14:50 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-25 14:49 [PATCH v2 00/28] spi: s3c64xx: winter cleanup and gs101 support Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 01/28] spi: s3c64xx: explicitly include <linux/io.h> Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 18:58 ` Sam Protsenko 2024-01-25 18:58 ` Sam Protsenko 2024-01-26 14:40 ` Tudor Ambarus 2024-01-26 14:40 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 02/28] spi: s3c64xx: explicitly include <linux/bits.h> Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 03/28] spi: s3c64xx: avoid possible negative array index Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 18:50 ` Sam Protsenko 2024-01-25 18:50 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 04/28] spi: dt-bindings: samsung: add google,gs101-spi compatible Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 05/28] spi: dt-bindings: samsung: add samsung,spi-fifosize property Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 16:16 ` Mark Brown 2024-01-25 16:16 ` Mark Brown 2024-01-25 16:38 ` Tudor Ambarus 2024-01-25 16:38 ` Tudor Ambarus 2024-01-25 17:26 ` Mark Brown 2024-01-25 17:26 ` Mark Brown 2024-01-25 17:30 ` Tudor Ambarus 2024-01-25 17:30 ` Tudor Ambarus 2024-01-25 17:45 ` Mark Brown 2024-01-25 17:45 ` Mark Brown 2024-01-25 19:01 ` Tudor Ambarus 2024-01-25 19:01 ` Tudor Ambarus 2024-01-30 22:25 ` Rob Herring 2024-01-30 22:25 ` Rob Herring 2024-02-05 9:42 ` Tudor Ambarus 2024-02-05 9:42 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 06/28] spi: s3c64xx: sort headers alphabetically Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 07/28] spi: s3c64xx: remove unneeded (void *) casts in of_match_table Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 19:04 ` Sam Protsenko 2024-01-25 19:04 ` Sam Protsenko 2024-01-26 8:24 ` Tudor Ambarus 2024-01-26 8:24 ` Tudor Ambarus 2024-01-26 19:40 ` Sam Protsenko 2024-01-26 19:40 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 08/28] spi: s3c64xx: remove else after return Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 09/28] spi: s3c64xx: use bitfield access macros Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 19:50 ` Sam Protsenko 2024-01-25 19:50 ` Sam Protsenko 2024-01-26 8:49 ` Tudor Ambarus 2024-01-26 8:49 ` Tudor Ambarus 2024-01-26 19:55 ` Sam Protsenko 2024-01-26 19:55 ` Sam Protsenko 2024-01-26 16:01 ` Tudor Ambarus 2024-01-26 16:01 ` Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus [this message] 2024-01-25 14:49 ` [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX, TX}_FIFO_LVL Tudor Ambarus 2024-01-25 20:03 ` Sam Protsenko 2024-01-25 20:03 ` Sam Protsenko 2024-01-25 21:48 ` Mark Brown 2024-01-25 21:48 ` Mark Brown 2024-01-26 8:51 ` Tudor Ambarus 2024-01-26 8:51 ` Tudor Ambarus 2024-01-26 8:12 ` Tudor Ambarus 2024-01-26 8:12 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 11/28] spi: s3c64xx: move common code outside if else Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:09 ` Sam Protsenko 2024-01-25 20:09 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 12/28] spi: s3c64xx: check return code of dmaengine_slave_config() Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:19 ` Sam Protsenko 2024-01-25 20:19 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 13/28] spi: s3c64xx: propagate the dma_submit_error() error code Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:23 ` Sam Protsenko 2024-01-25 20:23 ` Sam Protsenko 2024-01-26 7:42 ` Tudor Ambarus 2024-01-26 7:42 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 14/28] spi: s3c64xx: rename prepare_dma() to s3c64xx_prepare_dma() Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:24 ` Sam Protsenko 2024-01-25 20:24 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 15/28] spi: s3c64xx: return ETIMEDOUT for wait_for_completion_timeout() Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:30 ` Sam Protsenko 2024-01-25 20:30 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 16/28] spi: s3c64xx: simplify s3c64xx_wait_for_pio() Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:43 ` Sam Protsenko 2024-01-25 20:43 ` Sam Protsenko 2024-01-26 7:56 ` Tudor Ambarus 2024-01-26 7:56 ` Tudor Ambarus 2024-01-26 19:31 ` Sam Protsenko 2024-01-26 19:31 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 17/28] spi: s3c64xx: drop blank line between declarations Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:38 ` Sam Protsenko 2024-01-25 20:38 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 18/28] spi: s3c64xx: fix typo, s/configuartion/configuration Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:39 ` Sam Protsenko 2024-01-25 20:39 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 19/28] spi: s3c64xx: downgrade dev_warn to dev_dbg for optional dt props Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 20:40 ` Sam Protsenko 2024-01-25 20:40 ` Sam Protsenko 2024-01-25 14:49 ` [PATCH v2 20/28] spi: s3c64xx: add support for inferring fifosize from the compatible Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 14:49 ` [PATCH v2 21/28] spi: s3c64xx: infer " Tudor Ambarus 2024-01-25 14:49 ` Tudor Ambarus 2024-01-25 17:18 ` Mark Brown 2024-01-25 17:18 ` Mark Brown 2024-01-25 18:44 ` Tudor Ambarus 2024-01-25 18:44 ` Tudor Ambarus 2024-01-25 22:28 ` Sam Protsenko 2024-01-25 22:28 ` Sam Protsenko 2024-01-26 7:27 ` Tudor Ambarus 2024-01-26 7:27 ` Tudor Ambarus 2024-01-25 14:50 ` [PATCH v2 22/28] spi: s3c64xx: drop dependency on of_alias where possible Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus 2024-01-25 14:50 ` [PATCH v2 23/28] spi: s3c64xx: retrieve the FIFO size from the device tree Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus 2024-01-25 17:33 ` Mark Brown 2024-01-25 17:33 ` Mark Brown 2024-01-26 19:23 ` Sam Protsenko 2024-01-26 19:23 ` Sam Protsenko 2024-01-26 20:16 ` Arnd Bergmann 2024-01-26 20:16 ` Arnd Bergmann 2024-01-26 20:20 ` Sam Protsenko 2024-01-26 20:20 ` Sam Protsenko 2024-02-05 9:54 ` Tudor Ambarus 2024-02-05 9:54 ` Tudor Ambarus 2024-01-26 21:19 ` Mark Brown 2024-01-26 21:19 ` Mark Brown 2024-01-25 14:50 ` [PATCH v2 24/28] spi: s3c64xx: mark fifo_lvl_mask as deprecated Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus 2024-01-25 14:50 ` [PATCH v2 25/28] asm-generic/io.h: add iowrite{8,16}_32 accessors Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus 2024-01-25 17:41 ` Mark Brown 2024-01-25 17:41 ` Mark Brown 2024-01-25 21:23 ` Arnd Bergmann 2024-01-25 21:23 ` Arnd Bergmann 2024-01-26 7:21 ` Tudor Ambarus 2024-01-26 7:21 ` Tudor Ambarus 2024-01-25 14:50 ` [PATCH v2 26/28] spi: s3c64xx: add iowrite{8,16}_32_rep accessors Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus 2024-01-25 14:50 ` [PATCH v2 27/28] spi: s3c64xx: add support for google,gs101-spi Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus 2024-01-25 20:45 ` Sam Protsenko 2024-01-25 20:45 ` Sam Protsenko 2024-01-25 14:50 ` [PATCH v2 28/28] MAINTAINERS: add Tudor Ambarus as R for the samsung SPI driver Tudor Ambarus 2024-01-25 14:50 ` Tudor Ambarus
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