From: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH 2/4] drm/xe: add bind time pat index to xe_bo structure Date: Tue, 30 Jan 2024 21:36:50 +0200 [thread overview] Message-ID: <20240130193652.374270-3-juhapekka.heikkila@gmail.com> (raw) In-Reply-To: <20240130193652.374270-1-juhapekka.heikkila@gmail.com> Add BO bind time pat index member to xe_bo structure and store pat index from xe_vma to xe_bo. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/xe/xe_bo_types.h | 12 ++++++++++++ drivers/gpu/drm/xe/xe_pt.c | 22 ++++++++++++++++++---- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h index 14ef13b7b421..6d599f1e846b 100644 --- a/drivers/gpu/drm/xe/xe_bo_types.h +++ b/drivers/gpu/drm/xe/xe_bo_types.h @@ -91,6 +91,18 @@ struct xe_bo { /** @vram_userfault_link: Link into @mem_access.vram_userfault.list */ struct list_head vram_userfault_link; + + /** + * @pat_index: The pat index requested when bind this BO + */ + u16 pat_index; + + /** + * @has_sealed_pat_index: The pat index is sealed because this BO is + * pinned as framebuffer. This is to prevent flipping compression + * on/off from framebuffers while in use. + */ + bool has_sealed_pat_index; }; #define intel_bo_to_drm_bo(bo) (&(bo)->ttm.base) diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index de1030a47588..c72cb75d993c 100644 --- a/drivers/gpu/drm/xe/xe_pt.c +++ b/drivers/gpu/drm/xe/xe_pt.c @@ -1208,10 +1208,11 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue struct dma_fence *fence; struct invalidation_fence *ifence = NULL; struct xe_range_fence *rfence; + struct xe_bo *bo = xe_vma_bo(vma); int err; bind_pt_update.locked = false; - xe_bo_assert_held(xe_vma_bo(vma)); + xe_bo_assert_held(bo); xe_vm_assert_held(vm); vm_dbg(&xe_vma_vm(vma)->xe->drm, @@ -1252,8 +1253,21 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue return ERR_PTR(-ENOMEM); } + /* + * On Xe2 BO which was pinned as framebuffer before with different + * PAT index cannot be bound with different PAT index. This is + * to prevent switching CCS on/off from framebuffers on the fly + * with Xe2. + */ + if (bo) { + if (bo->has_sealed_pat_index && bo->pat_index != vma->pat_index) + return ERR_PTR(-EINVAL); + + bo->pat_index = vma->pat_index; + } + fence = xe_migrate_update_pgtables(tile->migrate, - vm, xe_vma_bo(vma), q, + vm, bo, q, entries, num_entries, syncs, num_syncs, &bind_pt_update.base); @@ -1287,8 +1301,8 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue DMA_RESV_USAGE_KERNEL : DMA_RESV_USAGE_BOOKKEEP); - if (!xe_vma_has_no_bo(vma) && !xe_vma_bo(vma)->vm) - dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence, + if (!xe_vma_has_no_bo(vma) && !bo->vm) + dma_resv_add_fence(bo->ttm.base.resv, fence, DMA_RESV_USAGE_BOOKKEEP); xe_pt_commit_bind(vma, entries, num_entries, rebind, bind_pt_update.locked ? &deferred : NULL); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Subject: [PATCH 2/4] drm/xe: add bind time pat index to xe_bo structure Date: Tue, 30 Jan 2024 21:36:50 +0200 [thread overview] Message-ID: <20240130193652.374270-3-juhapekka.heikkila@gmail.com> (raw) In-Reply-To: <20240130193652.374270-1-juhapekka.heikkila@gmail.com> Add BO bind time pat index member to xe_bo structure and store pat index from xe_vma to xe_bo. Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/xe/xe_bo_types.h | 12 ++++++++++++ drivers/gpu/drm/xe/xe_pt.c | 22 ++++++++++++++++++---- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h index 14ef13b7b421..6d599f1e846b 100644 --- a/drivers/gpu/drm/xe/xe_bo_types.h +++ b/drivers/gpu/drm/xe/xe_bo_types.h @@ -91,6 +91,18 @@ struct xe_bo { /** @vram_userfault_link: Link into @mem_access.vram_userfault.list */ struct list_head vram_userfault_link; + + /** + * @pat_index: The pat index requested when bind this BO + */ + u16 pat_index; + + /** + * @has_sealed_pat_index: The pat index is sealed because this BO is + * pinned as framebuffer. This is to prevent flipping compression + * on/off from framebuffers while in use. + */ + bool has_sealed_pat_index; }; #define intel_bo_to_drm_bo(bo) (&(bo)->ttm.base) diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index de1030a47588..c72cb75d993c 100644 --- a/drivers/gpu/drm/xe/xe_pt.c +++ b/drivers/gpu/drm/xe/xe_pt.c @@ -1208,10 +1208,11 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue struct dma_fence *fence; struct invalidation_fence *ifence = NULL; struct xe_range_fence *rfence; + struct xe_bo *bo = xe_vma_bo(vma); int err; bind_pt_update.locked = false; - xe_bo_assert_held(xe_vma_bo(vma)); + xe_bo_assert_held(bo); xe_vm_assert_held(vm); vm_dbg(&xe_vma_vm(vma)->xe->drm, @@ -1252,8 +1253,21 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue return ERR_PTR(-ENOMEM); } + /* + * On Xe2 BO which was pinned as framebuffer before with different + * PAT index cannot be bound with different PAT index. This is + * to prevent switching CCS on/off from framebuffers on the fly + * with Xe2. + */ + if (bo) { + if (bo->has_sealed_pat_index && bo->pat_index != vma->pat_index) + return ERR_PTR(-EINVAL); + + bo->pat_index = vma->pat_index; + } + fence = xe_migrate_update_pgtables(tile->migrate, - vm, xe_vma_bo(vma), q, + vm, bo, q, entries, num_entries, syncs, num_syncs, &bind_pt_update.base); @@ -1287,8 +1301,8 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue DMA_RESV_USAGE_KERNEL : DMA_RESV_USAGE_BOOKKEEP); - if (!xe_vma_has_no_bo(vma) && !xe_vma_bo(vma)->vm) - dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence, + if (!xe_vma_has_no_bo(vma) && !bo->vm) + dma_resv_add_fence(bo->ttm.base.resv, fence, DMA_RESV_USAGE_BOOKKEEP); xe_pt_commit_bind(vma, entries, num_entries, rebind, bind_pt_update.locked ? &deferred : NULL); -- 2.25.1
next prev parent reply other threads:[~2024-01-30 19:38 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-30 19:36 [PATCH 0/4] Enable ccs compressed framebuffers on Xe2 Juha-Pekka Heikkila 2024-01-30 19:36 ` Juha-Pekka Heikkila 2024-01-30 19:36 ` [PATCH 1/4] drm/xe/pat: annotate pat index table with compression info Juha-Pekka Heikkila 2024-01-30 19:36 ` Juha-Pekka Heikkila 2024-01-31 5:32 ` Ghimiray, Himal Prasad 2024-01-30 19:36 ` Juha-Pekka Heikkila [this message] 2024-01-30 19:36 ` [PATCH 2/4] drm/xe: add bind time pat index to xe_bo structure Juha-Pekka Heikkila 2024-01-31 6:02 ` Ghimiray, Himal Prasad 2024-01-31 18:56 ` Matt Roper 2024-02-01 14:17 ` Juha-Pekka Heikkila 2024-02-01 15:02 ` Juha-Pekka Heikkila 2024-01-30 19:36 ` [PATCH 3/4] drm/xe/xe2: Limit ccs framebuffers to tile4 only Juha-Pekka Heikkila 2024-01-30 19:36 ` Juha-Pekka Heikkila 2024-01-31 11:40 ` Ville Syrjälä 2024-01-31 12:09 ` Ville Syrjälä 2024-01-30 19:36 ` [PATCH 4/4] drm/i915/display: On Xe2 always enable decompression with tile4 Juha-Pekka Heikkila 2024-01-30 19:36 ` Juha-Pekka Heikkila 2024-01-31 2:06 ` ✓ CI.Patch_applied: success for Enable ccs compressed framebuffers on Xe2 (rev5) Patchwork 2024-01-31 2:07 ` ✓ CI.checkpatch: " Patchwork 2024-01-31 2:07 ` ✓ CI.KUnit: " Patchwork 2024-01-31 2:15 ` ✓ CI.Build: " Patchwork 2024-01-31 2:15 ` ✓ CI.Hooks: " Patchwork 2024-01-31 2:16 ` ✗ CI.checksparse: warning " Patchwork 2024-01-31 3:01 ` ✓ CI.BAT: success " Patchwork 2024-02-02 5:26 ` ✓ Fi.CI.BAT: success for Enable ccs compressed framebuffers on Xe2 (rev6) Patchwork 2024-02-02 7:09 ` ✗ Fi.CI.IGT: failure " Patchwork
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