[PATCH RFC 2/3] clk: renesas: rzg2l: Add disable_sync() callback

[Biju Das <biju.das.jz@bp.renesas.com>]

Add disable_sync() callback to synchronize clk gating operation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3d2daa4ba2a4..7baf0d7217e2 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1277,6 +1277,28 @@ static void rzg2l_mod_clock_disable(struct clk_hw *hw)
 	rzg2l_mod_clock_endisable(hw, false);
 }
 
+static void rzg2l_mod_clock_disable_sync(struct clk_hw *hw)
+{
+	struct mstp_clock *clock = to_mod_clock(hw);
+	struct rzg2l_cpg_priv *priv = clock->priv;
+	struct device *dev = priv->dev;
+	unsigned int reg = clock->off;
+	u32 bitmask = BIT(clock->bit);
+	u32 value;
+	int error;
+
+	rzg2l_mod_clock_disable(hw);
+
+	if (!priv->info->has_clk_mon_regs)
+		return;
+
+	error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
+					  !(value & bitmask), 0, 10);
+	if (error)
+		dev_err(dev, "Failed to disable CLK %p\n",
+			priv->base + CLK_ON_R(reg));
+}
+
 static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
 {
 	struct mstp_clock *clock = to_mod_clock(hw);
@@ -1303,6 +1325,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
 static const struct clk_ops rzg2l_mod_clock_ops = {
 	.enable = rzg2l_mod_clock_enable,
 	.disable = rzg2l_mod_clock_disable,
+	.disable_sync = rzg2l_mod_clock_disable_sync,
 	.is_enabled = rzg2l_mod_clock_is_enabled,
 };
 
-- 
2.25.1