From: Charles Perry <charles.perry@savoirfairelinux.com> To: mdf@kernel.org Cc: avandiver@markem-imaje.com, bcody@markem-imaje.com, Charles Perry <charles.perry@savoirfairelinux.com>, Wu Hao <hao.wu@intel.com>, Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michal Simek <michal.simek@amd.com>, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Date: Wed, 31 Jan 2024 18:05:32 -0500 [thread overview] Message-ID: <20240131230542.3993409-3-charles.perry@savoirfairelinux.com> (raw) In-Reply-To: <20240131230542.3993409-1-charles.perry@savoirfairelinux.com> Document the slave SelectMAP interface of Xilinx 7 series FPGA. Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com> --- .../bindings/fpga/xlnx,fpga-selectmap.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml new file mode 100644 index 0000000000000..c9a446b43cdd9 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SelectMAP FPGA interface + +maintainers: + - Charles Perry <charles.perry@savoirfairelinux.com> + +description: | + Xilinx 7 Series FPGAs support a method of loading the bitstream over a + parallel port named the SelectMAP interface in the documentation. Only + the x8 mode is supported where data is loaded at one byte per rising edge of + the clock, with the MSB of each byte presented to the D0 pin. + + Datasheets: + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf + +allOf: + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + +properties: + compatible: + enum: + - xlnx,fpga-selectmap + + reg: + description: + At least 1 byte of memory mapped IO + maxItems: 1 + + prog-gpios: + description: + config pin (referred to as PROGRAM_B in the manual) + maxItems: 1 + + done-gpios: + description: + config status pin (referred to as DONE in the manual) + maxItems: 1 + + init-gpios: + description: + initialization status and configuration error pin + (referred to as INIT_B in the manual) + maxItems: 1 + + csi-gpios: + description: + chip select pin (referred to as CSI_B in the manual) + Optional gpio for if the bus controller does not provide a chip select. + maxItems: 1 + + rdwr-gpios: + description: + read/write select pin (referred to as RDWR_B in the manual) + Optional gpio for if the bus controller does not provide this pin. + maxItems: 1 + +required: + - compatible + - reg + - prog-gpios + - done-gpios + - init-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + fpga-mgr@8000000 { + compatible = "xlnx,fpga-selectmap"; + reg = <0x8000000 0x4>; + prog-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + init-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + csi-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + rdwr-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; +... -- 2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Charles Perry <charles.perry@savoirfairelinux.com> To: mdf@kernel.org Cc: avandiver@markem-imaje.com, bcody@markem-imaje.com, Charles Perry <charles.perry@savoirfairelinux.com>, Wu Hao <hao.wu@intel.com>, Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michal Simek <michal.simek@amd.com>, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Date: Wed, 31 Jan 2024 18:05:32 -0500 [thread overview] Message-ID: <20240131230542.3993409-3-charles.perry@savoirfairelinux.com> (raw) In-Reply-To: <20240131230542.3993409-1-charles.perry@savoirfairelinux.com> Document the slave SelectMAP interface of Xilinx 7 series FPGA. Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com> --- .../bindings/fpga/xlnx,fpga-selectmap.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml new file mode 100644 index 0000000000000..c9a446b43cdd9 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SelectMAP FPGA interface + +maintainers: + - Charles Perry <charles.perry@savoirfairelinux.com> + +description: | + Xilinx 7 Series FPGAs support a method of loading the bitstream over a + parallel port named the SelectMAP interface in the documentation. Only + the x8 mode is supported where data is loaded at one byte per rising edge of + the clock, with the MSB of each byte presented to the D0 pin. + + Datasheets: + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf + +allOf: + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + +properties: + compatible: + enum: + - xlnx,fpga-selectmap + + reg: + description: + At least 1 byte of memory mapped IO + maxItems: 1 + + prog-gpios: + description: + config pin (referred to as PROGRAM_B in the manual) + maxItems: 1 + + done-gpios: + description: + config status pin (referred to as DONE in the manual) + maxItems: 1 + + init-gpios: + description: + initialization status and configuration error pin + (referred to as INIT_B in the manual) + maxItems: 1 + + csi-gpios: + description: + chip select pin (referred to as CSI_B in the manual) + Optional gpio for if the bus controller does not provide a chip select. + maxItems: 1 + + rdwr-gpios: + description: + read/write select pin (referred to as RDWR_B in the manual) + Optional gpio for if the bus controller does not provide this pin. + maxItems: 1 + +required: + - compatible + - reg + - prog-gpios + - done-gpios + - init-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + fpga-mgr@8000000 { + compatible = "xlnx,fpga-selectmap"; + reg = <0x8000000 0x4>; + prog-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + init-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + csi-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + rdwr-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; +... -- 2.43.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-31 23:06 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-29 22:56 [PATCH 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry 2024-01-29 22:56 ` [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Charles Perry 2024-01-30 0:21 ` Rob Herring 2024-01-30 7:52 ` Krzysztof Kozlowski 2024-01-30 7:53 ` Krzysztof Kozlowski 2024-01-30 15:45 ` Charles Perry 2024-01-30 16:05 ` Krzysztof Kozlowski 2024-01-30 17:05 ` Charles Perry 2024-01-30 17:58 ` Krzysztof Kozlowski 2024-01-30 23:32 ` Charles Perry 2024-01-30 16:09 ` Krzysztof Kozlowski 2024-01-31 11:03 ` Kris Chaplin 2024-02-04 8:30 ` Xu Yilun 2024-02-13 21:54 ` Charles Perry 2024-01-29 22:56 ` [PATCH 3/3] fpga: xilinx-selectmap: add new driver Charles Perry 2024-01-30 7:56 ` Krzysztof Kozlowski 2024-01-31 23:05 ` [PATCH 0/3] " Charles Perry 2024-01-31 23:05 ` Charles Perry 2024-01-31 23:05 ` [PATCH 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry 2024-01-31 23:05 ` Charles Perry 2024-02-04 8:22 ` Xu Yilun 2024-02-04 8:22 ` Xu Yilun 2024-02-06 15:39 ` Charles Perry 2024-02-06 15:39 ` Charles Perry 2024-01-31 23:05 ` Charles Perry [this message] 2024-01-31 23:05 ` [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Charles Perry 2024-02-01 8:07 ` Krzysztof Kozlowski 2024-02-01 8:07 ` Krzysztof Kozlowski 2024-02-01 18:24 ` Charles Perry 2024-02-01 18:24 ` Charles Perry 2024-02-02 10:49 ` Krzysztof Kozlowski 2024-02-02 10:49 ` Krzysztof Kozlowski 2024-02-02 19:52 ` Charles Perry 2024-02-02 19:52 ` Charles Perry 2024-01-31 23:05 ` [PATCH 3/3] fpga: xilinx-selectmap: add new driver Charles Perry 2024-01-31 23:05 ` Charles Perry 2024-02-04 8:10 ` Xu Yilun 2024-02-04 8:10 ` Xu Yilun 2024-02-06 15:48 ` Charles Perry 2024-02-06 15:48 ` Charles Perry 2024-02-02 20:16 ` [PATCH 0/3] " Rob Herring 2024-02-02 20:16 ` Rob Herring 2024-02-02 20:53 ` Charles Perry 2024-02-02 20:53 ` Charles Perry
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