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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent
Date: Mon,  5 Feb 2024 12:41:05 +0000	[thread overview]
Message-ID: <20240205124135.14779-19-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Samuel Holland <samuel@sholland.org>

commit e91033621d56e055803c4c4ba507fbbb2d145a7f upstream.

The RISC-V PLIC binding uses interrupts-extended to specify its parent
domain(s). That binding does not allow the interrupt-parent property to
appear in the irqchip node. This prevents of_irq_init from properly
detecting the irqchip hierarchy.

If no interrupt-parent property is present in the enclosing bus or root
node, then desc->interrupt_parent will be NULL for both the per-CPU
RISC-V INTC (the actual root domain) and the RISC-V PLIC. Similarly, if
the bus or root node specifies `interrupt-parent = <&plic>`, then
of_irq_init will hit the `desc->interrupt_parent == np` check, and again
all parents will be NULL. So things happen to work today for some boards
due to Makefile ordering.

However, things break when another irqchip ("foo") is stacked on top of
the PLIC. The bus or root node will have `interrupt-parent = <&foo>`,
since that is what all of the other peripherals need. When of_irq_init
runs, it will try to find the PLIC's parent domain. of_irq_find_parent
will fall back to using the interrupt-parent property of the PLIC's
parent node (i.e. the bus or root node), and of_irq_init will see "foo"
as the PLIC's parent domain. But this is wrong, because "foo" is
actually the PLIC's child domain!

So of_irq_init wrongly attempts to init the stacked irqchip before the
PLIC. This fails and breaks booting.

Fix this by using the first node referenced by interrupts-extended as
the parent when that property is present. This allows of_irq_init to see
the relationship between the PLIC and the per-CPU RISC-V INTC, and thus
only the RISC-V INTC is (correctly) considered a root domain.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220412051529.6293-1-samuel@sholland.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/of/irq.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 352e14b007e7..7f84e7649dc5 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -507,9 +507,18 @@ void __init of_irq_init(const struct of_device_id *matches)
 
 		desc->irq_init_cb = match->data;
 		desc->dev = of_node_get(np);
-		desc->interrupt_parent = of_irq_find_parent(np);
-		if (desc->interrupt_parent == np)
+		/*
+		 * interrupts-extended can reference multiple parent domains.
+		 * Arbitrarily pick the first one; assume any other parents
+		 * are the same distance away from the root irq controller.
+		 */
+		desc->interrupt_parent = of_parse_phandle(np, "interrupts-extended", 0);
+		if (!desc->interrupt_parent)
+			desc->interrupt_parent = of_irq_find_parent(np);
+		if (desc->interrupt_parent == np) {
+			of_node_put(desc->interrupt_parent);
 			desc->interrupt_parent = NULL;
+		}
 		list_add_tail(&desc->list, &intc_desc_list);
 	}
 
-- 
2.34.1



  parent reply	other threads:[~2024-02-05 12:42 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
2024-02-06  9:18   ` nobuhiro1.iwamatsu
2024-02-06  9:52     ` Prabhakar Mahadev Lad
2024-02-06 10:12       ` Pavel Machek
2024-02-06 11:42         ` Prabhakar Mahadev Lad
2024-02-05 12:41 ` [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
2024-02-05 12:41 ` Lad Prabhakar [this message]
2024-02-05 12:41 ` [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
2024-02-05 19:36   ` Pavel Machek
2024-02-05 12:41 ` [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
2024-02-05 19:33 ` [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek
2024-02-06  8:20 ` nobuhiro1.iwamatsu
2024-02-06  8:29 ` Pavel Machek
2024-02-06  9:02   ` Prabhakar Mahadev Lad
2024-02-06  9:08     ` Pavel Machek

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