All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
Date: Mon,  5 Feb 2024 12:41:13 +0000	[thread overview]
Message-ID: <20240205124135.14779-27-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 3aff0403f814df6ce2377a6ecf61dd7750a3925f upstream.

Having a clocksource_arch_init() callback always sets vdso_clock_mode to
VDSO_CLOCKMODE_ARCHTIMER if GENERIC_GETTIMEOFDAY is enabled, this is
required for the riscv-timer.

This works for platforms where just riscv-timer clocksource is present.
On platforms where other clock sources are available we want them to
register with vdso_clock_mode set to VDSO_CLOCKMODE_NONE.

On the Renesas RZ/Five SoC OSTM block can be used as clocksource [0], to
avoid multiple clock sources being registered as VDSO_CLOCKMODE_ARCHTIMER
move setting of vdso_clock_mode in the riscv-timer driver instead of doing
this in clocksource_arch_init() callback as done similarly for ARM/64
architecture.

[0] drivers/clocksource/renesas-ostm.c

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221229224601.103851-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/riscv/Kconfig                | 1 -
 arch/riscv/kernel/time.c          | 9 ---------
 drivers/clocksource/timer-riscv.c | 5 +++++
 3 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6cdfb41a9181..6b28e663fbed 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -12,7 +12,6 @@ config 32BIT
 
 config RISCV
 	def_bool y
-	select ARCH_CLOCKSOURCE_INIT
 	select ARCH_SUPPORTS_ATOMIC_RMW
 	select ARCH_HAS_BINFMT_FLAT
 	select ARCH_HAS_DEBUG_VM_PGTABLE
diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
index 303ae47dfb4d..726860a490f3 100644
--- a/arch/riscv/kernel/time.c
+++ b/arch/riscv/kernel/time.c
@@ -32,12 +32,3 @@ void __init time_init(void)
 
 	tick_setup_hrtimer_broadcast();
 }
-
-void clocksource_arch_init(struct clocksource *cs)
-{
-#ifdef CONFIG_GENERIC_GETTIMEOFDAY
-	cs->vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER;
-#else
-	cs->vdso_clock_mode = VDSO_CLOCKMODE_NONE;
-#endif
-}
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index a035bdf6fc58..a8210493cc21 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -58,6 +58,11 @@ static struct clocksource riscv_clocksource = {
 	.mask		= CLOCKSOURCE_MASK(64),
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 	.read		= riscv_clocksource_rdtime,
+#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
+	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
+#else
+	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
+#endif
 };
 
 static int riscv_timer_starting_cpu(unsigned int cpu)
-- 
2.34.1



  parent reply	other threads:[~2024-02-05 12:42 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
2024-02-06  9:18   ` nobuhiro1.iwamatsu
2024-02-06  9:52     ` Prabhakar Mahadev Lad
2024-02-06 10:12       ` Pavel Machek
2024-02-06 11:42         ` Prabhakar Mahadev Lad
2024-02-05 12:41 ` [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
2024-02-05 12:41 ` Lad Prabhakar [this message]
2024-02-05 12:41 ` [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
2024-02-05 19:36   ` Pavel Machek
2024-02-05 12:41 ` [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
2024-02-05 19:33 ` [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek
2024-02-06  8:20 ` nobuhiro1.iwamatsu
2024-02-06  8:29 ` Pavel Machek
2024-02-06  9:02   ` Prabhakar Mahadev Lad
2024-02-06  9:08     ` Pavel Machek

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240205124135.14779-27-prabhakar.mahadev-lad.rj@bp.renesas.com \
    --to=prabhakar.mahadev-lad.rj@bp.renesas.com \
    --cc=biju.das.jz@bp.renesas.com \
    --cc=cip-dev@lists.cip-project.org \
    --cc=nobuhiro1.iwamatsu@toshiba.co.jp \
    --cc=pavel@denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.