From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions
Date: Mon, 5 Feb 2024 12:41:17 +0000 [thread overview]
Message-ID: <20240205124135.14779-31-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 668d361c9d893be3cbd4f3650e1934a62b204def upstream.
Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
amend the RZ/Five CPG clock and reset definitions.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220622181723.13033-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index 27e232733096..77cde8effdc7 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -108,6 +108,15 @@
#define R9A07G043_ADC_ADCLK 76
#define R9A07G043_ADC_PCLK 77
#define R9A07G043_TSU_PCLK 78
+#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
+#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
+#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
+#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */
+#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */
+#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */
+#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */
+#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */
+#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */
/* R9A07G043 Resets */
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
@@ -180,5 +189,16 @@
#define R9A07G043_ADC_PRESETN 67
#define R9A07G043_ADC_ADRST_N 68
#define R9A07G043_TSU_PRESETN 69
+#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */
+#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */
+#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */
+#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */
+#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */
+#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */
+#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */
+#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */
+#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
+#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
--
2.34.1
next prev parent reply other threads:[~2024-02-05 12:42 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
2024-02-06 9:18 ` nobuhiro1.iwamatsu
2024-02-06 9:52 ` Prabhakar Mahadev Lad
2024-02-06 10:12 ` Pavel Machek
2024-02-06 11:42 ` Prabhakar Mahadev Lad
2024-02-05 12:41 ` [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2024-02-05 12:41 ` Lad Prabhakar [this message]
2024-02-05 12:41 ` [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
2024-02-05 19:36 ` Pavel Machek
2024-02-05 12:41 ` [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
2024-02-05 19:33 ` [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek
2024-02-06 8:20 ` nobuhiro1.iwamatsu
2024-02-06 8:29 ` Pavel Machek
2024-02-06 9:02 ` Prabhakar Mahadev Lad
2024-02-06 9:08 ` Pavel Machek
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