From: <gabriel.fernandez@foss.st.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v9 4/4] arm64: dts: st: add rcc support for STM32MP25
Date: Thu, 8 Feb 2024 15:23:01 +0100 [thread overview]
Message-ID: <20240208142301.155698-5-gabriel.fernandez@foss.st.com> (raw)
In-Reply-To: <20240208142301.155698-1-gabriel.fernandez@foss.st.com>
From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Add RCC support to manage clocks and resets on the STM32MP25.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 144 ++++++++++++++++++-------
arch/arm64/boot/dts/st/stm32mp255.dtsi | 4 +-
2 files changed, 110 insertions(+), 38 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 5dd4f3580a60..15b79d26d1c6 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -3,7 +3,9 @@
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
+#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/st,stm32mp25-rcc.h>
/ {
#address-cells = <2>;
@@ -35,34 +37,16 @@ arm_wdt: watchdog {
};
clocks {
- ck_flexgen_08: ck-flexgen-08 {
+ clk_dsi_txbyte: txbyteclk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <100000000>;
+ clock-frequency = <0>;
};
- ck_flexgen_51: ck-flexgen-51 {
+ clk_rcbsec: clk-rcbsec {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_ls_mcu: ck-icn-ls-mcu {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_p_vdec: ck-icn-p-vdec {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_p_venc: ck-icn-p-venc {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
+ clock-frequency = <64000000>;
};
};
@@ -134,7 +118,7 @@ usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_flexgen_08>;
+ clocks = <&rcc CK_KER_USART2>;
status = "disabled";
};
@@ -143,8 +127,9 @@ sdmmc1: mmc@48220000 {
arm,primecell-periphid = <0x00353180>;
reg = <0x48220000 0x400>, <0x44230400 0x8>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_flexgen_51>;
+ clocks = <&rcc CK_KER_SDMMC1 >;
clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
@@ -168,6 +153,93 @@ package_otp@1e8 {
};
};
+ rcc: clock-controller@44200000 {
+ compatible = "st,stm32mp25-rcc";
+ reg = <0x44200000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_MSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>,
+ <&scmi_clk CK_SCMI_HSE_DIV2>,
+ <&scmi_clk CK_SCMI_ICN_HS_MCU>,
+ <&scmi_clk CK_SCMI_ICN_LS_MCU>,
+ <&scmi_clk CK_SCMI_ICN_SDMMC>,
+ <&scmi_clk CK_SCMI_ICN_DDR>,
+ <&scmi_clk CK_SCMI_ICN_DISPLAY>,
+ <&scmi_clk CK_SCMI_ICN_HSL>,
+ <&scmi_clk CK_SCMI_ICN_NIC>,
+ <&scmi_clk CK_SCMI_ICN_VID>,
+ <&scmi_clk CK_SCMI_FLEXGEN_07>,
+ <&scmi_clk CK_SCMI_FLEXGEN_08>,
+ <&scmi_clk CK_SCMI_FLEXGEN_09>,
+ <&scmi_clk CK_SCMI_FLEXGEN_10>,
+ <&scmi_clk CK_SCMI_FLEXGEN_11>,
+ <&scmi_clk CK_SCMI_FLEXGEN_12>,
+ <&scmi_clk CK_SCMI_FLEXGEN_13>,
+ <&scmi_clk CK_SCMI_FLEXGEN_14>,
+ <&scmi_clk CK_SCMI_FLEXGEN_15>,
+ <&scmi_clk CK_SCMI_FLEXGEN_16>,
+ <&scmi_clk CK_SCMI_FLEXGEN_17>,
+ <&scmi_clk CK_SCMI_FLEXGEN_18>,
+ <&scmi_clk CK_SCMI_FLEXGEN_19>,
+ <&scmi_clk CK_SCMI_FLEXGEN_20>,
+ <&scmi_clk CK_SCMI_FLEXGEN_21>,
+ <&scmi_clk CK_SCMI_FLEXGEN_22>,
+ <&scmi_clk CK_SCMI_FLEXGEN_23>,
+ <&scmi_clk CK_SCMI_FLEXGEN_24>,
+ <&scmi_clk CK_SCMI_FLEXGEN_25>,
+ <&scmi_clk CK_SCMI_FLEXGEN_26>,
+ <&scmi_clk CK_SCMI_FLEXGEN_27>,
+ <&scmi_clk CK_SCMI_FLEXGEN_28>,
+ <&scmi_clk CK_SCMI_FLEXGEN_29>,
+ <&scmi_clk CK_SCMI_FLEXGEN_30>,
+ <&scmi_clk CK_SCMI_FLEXGEN_31>,
+ <&scmi_clk CK_SCMI_FLEXGEN_32>,
+ <&scmi_clk CK_SCMI_FLEXGEN_33>,
+ <&scmi_clk CK_SCMI_FLEXGEN_34>,
+ <&scmi_clk CK_SCMI_FLEXGEN_35>,
+ <&scmi_clk CK_SCMI_FLEXGEN_36>,
+ <&scmi_clk CK_SCMI_FLEXGEN_37>,
+ <&scmi_clk CK_SCMI_FLEXGEN_38>,
+ <&scmi_clk CK_SCMI_FLEXGEN_39>,
+ <&scmi_clk CK_SCMI_FLEXGEN_40>,
+ <&scmi_clk CK_SCMI_FLEXGEN_41>,
+ <&scmi_clk CK_SCMI_FLEXGEN_42>,
+ <&scmi_clk CK_SCMI_FLEXGEN_43>,
+ <&scmi_clk CK_SCMI_FLEXGEN_44>,
+ <&scmi_clk CK_SCMI_FLEXGEN_45>,
+ <&scmi_clk CK_SCMI_FLEXGEN_46>,
+ <&scmi_clk CK_SCMI_FLEXGEN_47>,
+ <&scmi_clk CK_SCMI_FLEXGEN_48>,
+ <&scmi_clk CK_SCMI_FLEXGEN_49>,
+ <&scmi_clk CK_SCMI_FLEXGEN_50>,
+ <&scmi_clk CK_SCMI_FLEXGEN_51>,
+ <&scmi_clk CK_SCMI_FLEXGEN_52>,
+ <&scmi_clk CK_SCMI_FLEXGEN_53>,
+ <&scmi_clk CK_SCMI_FLEXGEN_54>,
+ <&scmi_clk CK_SCMI_FLEXGEN_55>,
+ <&scmi_clk CK_SCMI_FLEXGEN_56>,
+ <&scmi_clk CK_SCMI_FLEXGEN_57>,
+ <&scmi_clk CK_SCMI_FLEXGEN_58>,
+ <&scmi_clk CK_SCMI_FLEXGEN_59>,
+ <&scmi_clk CK_SCMI_FLEXGEN_60>,
+ <&scmi_clk CK_SCMI_FLEXGEN_61>,
+ <&scmi_clk CK_SCMI_FLEXGEN_62>,
+ <&scmi_clk CK_SCMI_FLEXGEN_63>,
+ <&scmi_clk CK_SCMI_ICN_APB1>,
+ <&scmi_clk CK_SCMI_ICN_APB2>,
+ <&scmi_clk CK_SCMI_ICN_APB3>,
+ <&scmi_clk CK_SCMI_ICN_APB4>,
+ <&scmi_clk CK_SCMI_ICN_APBDBG>,
+ <&scmi_clk CK_SCMI_TIMG1>,
+ <&scmi_clk CK_SCMI_TIMG2>,
+ <&scmi_clk CK_SCMI_PLL3>,
+ <&clk_dsi_txbyte>;
+ };
+
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
@@ -186,7 +258,7 @@ gpioa: gpio@44240000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOA>;
st,bank-name = "GPIOA";
status = "disabled";
};
@@ -197,7 +269,7 @@ gpiob: gpio@44250000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOB>;
st,bank-name = "GPIOB";
status = "disabled";
};
@@ -208,7 +280,7 @@ gpioc: gpio@44260000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOC>;
st,bank-name = "GPIOC";
status = "disabled";
};
@@ -219,7 +291,7 @@ gpiod: gpio@44270000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x30000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOD>;
st,bank-name = "GPIOD";
status = "disabled";
};
@@ -230,7 +302,7 @@ gpioe: gpio@44280000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOE>;
st,bank-name = "GPIOE";
status = "disabled";
};
@@ -241,7 +313,7 @@ gpiof: gpio@44290000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x50000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOF>;
st,bank-name = "GPIOF";
status = "disabled";
};
@@ -252,7 +324,7 @@ gpiog: gpio@442a0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x60000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOG>;
st,bank-name = "GPIOG";
status = "disabled";
};
@@ -263,7 +335,7 @@ gpioh: gpio@442b0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x70000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOH>;
st,bank-name = "GPIOH";
status = "disabled";
};
@@ -274,7 +346,7 @@ gpioi: gpio@442c0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x80000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOI>;
st,bank-name = "GPIOI";
status = "disabled";
};
@@ -285,7 +357,7 @@ gpioj: gpio@442d0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x90000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
@@ -296,7 +368,7 @@ gpiok: gpio@442e0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa0000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
@@ -315,7 +387,7 @@ gpioz: gpio@46200000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 17f197c5b22b..d5175a1f339c 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -12,14 +12,14 @@ vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
reg = <0x480d0000 0x3c8>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_icn_p_vdec>;
+ clocks = <&rcc CK_BUS_VDEC>;
};
venc: venc@480e0000 {
compatible = "st,stm32mp25-venc";
reg = <0x480e0000 0x800>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&rcc CK_BUS_VENC>;
};
};
};
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: <gabriel.fernandez@foss.st.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v9 4/4] arm64: dts: st: add rcc support for STM32MP25
Date: Thu, 8 Feb 2024 15:23:01 +0100 [thread overview]
Message-ID: <20240208142301.155698-5-gabriel.fernandez@foss.st.com> (raw)
In-Reply-To: <20240208142301.155698-1-gabriel.fernandez@foss.st.com>
From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Add RCC support to manage clocks and resets on the STM32MP25.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 144 ++++++++++++++++++-------
arch/arm64/boot/dts/st/stm32mp255.dtsi | 4 +-
2 files changed, 110 insertions(+), 38 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 5dd4f3580a60..15b79d26d1c6 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -3,7 +3,9 @@
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
+#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/st,stm32mp25-rcc.h>
/ {
#address-cells = <2>;
@@ -35,34 +37,16 @@ arm_wdt: watchdog {
};
clocks {
- ck_flexgen_08: ck-flexgen-08 {
+ clk_dsi_txbyte: txbyteclk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <100000000>;
+ clock-frequency = <0>;
};
- ck_flexgen_51: ck-flexgen-51 {
+ clk_rcbsec: clk-rcbsec {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_ls_mcu: ck-icn-ls-mcu {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_p_vdec: ck-icn-p-vdec {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_p_venc: ck-icn-p-venc {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
+ clock-frequency = <64000000>;
};
};
@@ -134,7 +118,7 @@ usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_flexgen_08>;
+ clocks = <&rcc CK_KER_USART2>;
status = "disabled";
};
@@ -143,8 +127,9 @@ sdmmc1: mmc@48220000 {
arm,primecell-periphid = <0x00353180>;
reg = <0x48220000 0x400>, <0x44230400 0x8>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_flexgen_51>;
+ clocks = <&rcc CK_KER_SDMMC1 >;
clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
@@ -168,6 +153,93 @@ package_otp@1e8 {
};
};
+ rcc: clock-controller@44200000 {
+ compatible = "st,stm32mp25-rcc";
+ reg = <0x44200000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_MSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>,
+ <&scmi_clk CK_SCMI_HSE_DIV2>,
+ <&scmi_clk CK_SCMI_ICN_HS_MCU>,
+ <&scmi_clk CK_SCMI_ICN_LS_MCU>,
+ <&scmi_clk CK_SCMI_ICN_SDMMC>,
+ <&scmi_clk CK_SCMI_ICN_DDR>,
+ <&scmi_clk CK_SCMI_ICN_DISPLAY>,
+ <&scmi_clk CK_SCMI_ICN_HSL>,
+ <&scmi_clk CK_SCMI_ICN_NIC>,
+ <&scmi_clk CK_SCMI_ICN_VID>,
+ <&scmi_clk CK_SCMI_FLEXGEN_07>,
+ <&scmi_clk CK_SCMI_FLEXGEN_08>,
+ <&scmi_clk CK_SCMI_FLEXGEN_09>,
+ <&scmi_clk CK_SCMI_FLEXGEN_10>,
+ <&scmi_clk CK_SCMI_FLEXGEN_11>,
+ <&scmi_clk CK_SCMI_FLEXGEN_12>,
+ <&scmi_clk CK_SCMI_FLEXGEN_13>,
+ <&scmi_clk CK_SCMI_FLEXGEN_14>,
+ <&scmi_clk CK_SCMI_FLEXGEN_15>,
+ <&scmi_clk CK_SCMI_FLEXGEN_16>,
+ <&scmi_clk CK_SCMI_FLEXGEN_17>,
+ <&scmi_clk CK_SCMI_FLEXGEN_18>,
+ <&scmi_clk CK_SCMI_FLEXGEN_19>,
+ <&scmi_clk CK_SCMI_FLEXGEN_20>,
+ <&scmi_clk CK_SCMI_FLEXGEN_21>,
+ <&scmi_clk CK_SCMI_FLEXGEN_22>,
+ <&scmi_clk CK_SCMI_FLEXGEN_23>,
+ <&scmi_clk CK_SCMI_FLEXGEN_24>,
+ <&scmi_clk CK_SCMI_FLEXGEN_25>,
+ <&scmi_clk CK_SCMI_FLEXGEN_26>,
+ <&scmi_clk CK_SCMI_FLEXGEN_27>,
+ <&scmi_clk CK_SCMI_FLEXGEN_28>,
+ <&scmi_clk CK_SCMI_FLEXGEN_29>,
+ <&scmi_clk CK_SCMI_FLEXGEN_30>,
+ <&scmi_clk CK_SCMI_FLEXGEN_31>,
+ <&scmi_clk CK_SCMI_FLEXGEN_32>,
+ <&scmi_clk CK_SCMI_FLEXGEN_33>,
+ <&scmi_clk CK_SCMI_FLEXGEN_34>,
+ <&scmi_clk CK_SCMI_FLEXGEN_35>,
+ <&scmi_clk CK_SCMI_FLEXGEN_36>,
+ <&scmi_clk CK_SCMI_FLEXGEN_37>,
+ <&scmi_clk CK_SCMI_FLEXGEN_38>,
+ <&scmi_clk CK_SCMI_FLEXGEN_39>,
+ <&scmi_clk CK_SCMI_FLEXGEN_40>,
+ <&scmi_clk CK_SCMI_FLEXGEN_41>,
+ <&scmi_clk CK_SCMI_FLEXGEN_42>,
+ <&scmi_clk CK_SCMI_FLEXGEN_43>,
+ <&scmi_clk CK_SCMI_FLEXGEN_44>,
+ <&scmi_clk CK_SCMI_FLEXGEN_45>,
+ <&scmi_clk CK_SCMI_FLEXGEN_46>,
+ <&scmi_clk CK_SCMI_FLEXGEN_47>,
+ <&scmi_clk CK_SCMI_FLEXGEN_48>,
+ <&scmi_clk CK_SCMI_FLEXGEN_49>,
+ <&scmi_clk CK_SCMI_FLEXGEN_50>,
+ <&scmi_clk CK_SCMI_FLEXGEN_51>,
+ <&scmi_clk CK_SCMI_FLEXGEN_52>,
+ <&scmi_clk CK_SCMI_FLEXGEN_53>,
+ <&scmi_clk CK_SCMI_FLEXGEN_54>,
+ <&scmi_clk CK_SCMI_FLEXGEN_55>,
+ <&scmi_clk CK_SCMI_FLEXGEN_56>,
+ <&scmi_clk CK_SCMI_FLEXGEN_57>,
+ <&scmi_clk CK_SCMI_FLEXGEN_58>,
+ <&scmi_clk CK_SCMI_FLEXGEN_59>,
+ <&scmi_clk CK_SCMI_FLEXGEN_60>,
+ <&scmi_clk CK_SCMI_FLEXGEN_61>,
+ <&scmi_clk CK_SCMI_FLEXGEN_62>,
+ <&scmi_clk CK_SCMI_FLEXGEN_63>,
+ <&scmi_clk CK_SCMI_ICN_APB1>,
+ <&scmi_clk CK_SCMI_ICN_APB2>,
+ <&scmi_clk CK_SCMI_ICN_APB3>,
+ <&scmi_clk CK_SCMI_ICN_APB4>,
+ <&scmi_clk CK_SCMI_ICN_APBDBG>,
+ <&scmi_clk CK_SCMI_TIMG1>,
+ <&scmi_clk CK_SCMI_TIMG2>,
+ <&scmi_clk CK_SCMI_PLL3>,
+ <&clk_dsi_txbyte>;
+ };
+
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
@@ -186,7 +258,7 @@ gpioa: gpio@44240000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOA>;
st,bank-name = "GPIOA";
status = "disabled";
};
@@ -197,7 +269,7 @@ gpiob: gpio@44250000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOB>;
st,bank-name = "GPIOB";
status = "disabled";
};
@@ -208,7 +280,7 @@ gpioc: gpio@44260000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOC>;
st,bank-name = "GPIOC";
status = "disabled";
};
@@ -219,7 +291,7 @@ gpiod: gpio@44270000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x30000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOD>;
st,bank-name = "GPIOD";
status = "disabled";
};
@@ -230,7 +302,7 @@ gpioe: gpio@44280000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOE>;
st,bank-name = "GPIOE";
status = "disabled";
};
@@ -241,7 +313,7 @@ gpiof: gpio@44290000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x50000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOF>;
st,bank-name = "GPIOF";
status = "disabled";
};
@@ -252,7 +324,7 @@ gpiog: gpio@442a0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x60000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOG>;
st,bank-name = "GPIOG";
status = "disabled";
};
@@ -263,7 +335,7 @@ gpioh: gpio@442b0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x70000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOH>;
st,bank-name = "GPIOH";
status = "disabled";
};
@@ -274,7 +346,7 @@ gpioi: gpio@442c0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x80000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOI>;
st,bank-name = "GPIOI";
status = "disabled";
};
@@ -285,7 +357,7 @@ gpioj: gpio@442d0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x90000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
@@ -296,7 +368,7 @@ gpiok: gpio@442e0000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa0000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
@@ -315,7 +387,7 @@ gpioz: gpio@46200000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 17f197c5b22b..d5175a1f339c 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -12,14 +12,14 @@ vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
reg = <0x480d0000 0x3c8>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_icn_p_vdec>;
+ clocks = <&rcc CK_BUS_VDEC>;
};
venc: venc@480e0000 {
compatible = "st,stm32mp25-venc";
reg = <0x480e0000 0x800>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_icn_ls_mcu>;
+ clocks = <&rcc CK_BUS_VENC>;
};
};
};
--
2.25.1
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next prev parent reply other threads:[~2024-02-08 14:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-08 14:22 [PATCH v9 0/4] Introduce STM32MP257 clock driver gabriel.fernandez
2024-02-08 14:22 ` gabriel.fernandez
2024-02-08 14:22 ` [PATCH v9 1/4] clk: stm32mp13: use platform device APIs gabriel.fernandez
2024-02-08 14:22 ` gabriel.fernandez
2024-02-08 14:22 ` [PATCH v9 2/4] dt-bindings: stm32: update DT bingding for stm32mp25 gabriel.fernandez
2024-02-08 14:22 ` gabriel.fernandez
2024-02-08 18:06 ` Conor Dooley
2024-02-08 18:06 ` Conor Dooley
2024-02-09 9:46 ` Gabriel FERNANDEZ
2024-02-09 9:46 ` Gabriel FERNANDEZ
2024-02-09 17:02 ` Conor Dooley
2024-02-09 17:02 ` Conor Dooley
2024-02-08 14:23 ` [PATCH v9 3/4] clk: stm32: introduce clocks for STM32MP257 platform gabriel.fernandez
2024-02-08 14:23 ` gabriel.fernandez
2024-02-08 14:23 ` gabriel.fernandez [this message]
2024-02-08 14:23 ` [PATCH v9 4/4] arm64: dts: st: add rcc support for STM32MP25 gabriel.fernandez
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