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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Marc Zyngier <maz@kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Biju Das <biju.das.au@gmail.com>,
	linux-renesas-soc@vger.kernel.org
Subject: [PATCH 4/5] irqchip/renesas-rzg2l: Use TIEN for enable/disable
Date: Mon, 12 Feb 2024 11:37:11 +0000	[thread overview]
Message-ID: <20240212113712.71878-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com>

Use TIEN for enable/disable and avoid modifying TINT source selection
register.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzg2l.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index c48c8e836dd1..fbee400985a9 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -35,7 +35,6 @@
 #define TSSR(n)				(0x30 + ((n) * 4))
 #define TIEN				BIT(7)
 #define TSSEL_SHIFT(n)			(8 * (n))
-#define TSSEL_MASK			GENMASK(7, 0)
 #define IRQ_MASK			0x3
 
 #define TSSR_OFFSET(n)			((n) % 4)
@@ -178,8 +177,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d)
 
 		raw_spin_lock(&priv->lock);
 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
-		reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
-		writel_relaxed(reg, priv->base + TSSR(tssr_index));
+		rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, false);
 		raw_spin_unlock(&priv->lock);
 	}
 	irq_chip_disable_parent(d);
@@ -190,7 +188,6 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
 	unsigned int hw_irq = irqd_to_hwirq(d);
 
 	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
-		unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d);
 		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 		u32 offset = hw_irq - IRQC_TINT_START;
 		u32 tssr_offset = TSSR_OFFSET(offset);
@@ -199,8 +196,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
 
 		raw_spin_lock(&priv->lock);
 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
-		reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
-		writel_relaxed(reg, priv->base + TSSR(tssr_index));
+		rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, true);
 		raw_spin_unlock(&priv->lock);
 	}
 	irq_chip_enable_parent(d);
-- 
2.25.1


  parent reply	other threads:[~2024-02-12 11:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-12 11:37 [PATCH 0/5] Fix spurious TINT IRQ and enhancements Biju Das
2024-02-12 11:37 ` [PATCH 1/5] irqchip/renesas-rzg2l: Prevent IRQ HW race Biju Das
2024-03-01 14:39   ` Thomas Gleixner
2024-03-01 15:55     ` Biju Das
2024-02-12 11:37 ` [PATCH 2/5] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() Biju Das
2024-02-12 16:38   ` Geert Uytterhoeven
2024-02-12 17:06     ` Biju Das
2024-03-01 14:41     ` Thomas Gleixner
2024-02-12 11:37 ` [PATCH 3/5] irqchip/renesas-rzg2l: Fix spurious TINT IRQ Biju Das
2024-03-01 15:36   ` Thomas Gleixner
2024-03-05 17:41     ` Biju Das
2024-02-12 11:37 ` Biju Das [this message]
2024-03-01 14:15   ` [PATCH 4/5] irqchip/renesas-rzg2l: Use TIEN for enable/disable Thomas Gleixner
2024-03-01 14:43     ` Biju Das
2024-02-12 11:37 ` [PATCH 5/5] irqchip/renesas-rzg2l: Simplify rzg2l_irqc_irq_{en,dis}able() Biju Das
2024-03-01 14:08 ` [PATCH 0/5] Fix spurious TINT IRQ and enhancements Biju Das

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