From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com> Cc: Andrew Jones <ajones@ventanamicro.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan O'Rear <sorear@fastmail.com>, Samuel Holland <samuel.holland@sifive.com>, stable@vger.kernel.org Subject: [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Date: Mon, 12 Feb 2024 19:37:32 -0800 [thread overview] Message-ID: <20240213033744.4069020-2-samuel.holland@sifive.com> (raw) In-Reply-To: <20240213033744.4069020-1-samuel.holland@sifive.com> When the kernel is running in M-mode, the CBZE bit must be set in the menvcfg CSR, not in senvcfg. Cc: <stable@vger.kernel.org> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- (no changes since v1) arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com> Cc: Andrew Jones <ajones@ventanamicro.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan O'Rear <sorear@fastmail.com>, Samuel Holland <samuel.holland@sifive.com>, stable@vger.kernel.org Subject: [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Date: Mon, 12 Feb 2024 19:37:32 -0800 [thread overview] Message-ID: <20240213033744.4069020-2-samuel.holland@sifive.com> (raw) In-Reply-To: <20240213033744.4069020-1-samuel.holland@sifive.com> When the kernel is running in M-mode, the CBZE bit must be set in the menvcfg CSR, not in senvcfg. Cc: <stable@vger.kernel.org> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- (no changes since v1) arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE -- 2.43.0
next prev parent reply other threads:[~2024-02-13 3:37 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-13 3:37 [PATCH -fixes v2 0/4] riscv: cbo.zero fixes Samuel Holland 2024-02-13 3:37 ` Samuel Holland 2024-02-13 3:37 ` Samuel Holland [this message] 2024-02-13 3:37 ` [PATCH -fixes v2 1/4] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland 2024-02-13 3:37 ` [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions Samuel Holland 2024-02-13 3:37 ` Samuel Holland 2024-02-13 8:50 ` Krzysztof Kozlowski 2024-02-13 8:50 ` Krzysztof Kozlowski 2024-02-13 14:25 ` Andrew Jones 2024-02-13 14:25 ` Andrew Jones 2024-02-15 13:14 ` Conor Dooley 2024-02-15 13:14 ` Conor Dooley 2024-02-16 15:41 ` Stefan O'Rear 2024-02-16 15:41 ` Stefan O'Rear 2024-02-13 17:03 ` Conor Dooley 2024-02-13 17:03 ` Conor Dooley 2024-02-13 17:07 ` Conor Dooley 2024-02-13 17:07 ` Conor Dooley 2024-02-13 17:42 ` Stefan O'Rear 2024-02-13 17:42 ` Stefan O'Rear 2024-02-13 18:00 ` Samuel Holland 2024-02-13 18:00 ` Samuel Holland 2024-02-13 3:37 ` [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss Samuel Holland 2024-02-13 3:37 ` Samuel Holland 2024-02-13 15:14 ` Andrew Jones 2024-02-13 15:14 ` Andrew Jones 2024-02-13 17:52 ` Stefan O'Rear 2024-02-13 17:52 ` Stefan O'Rear 2024-02-13 18:18 ` Samuel Holland 2024-02-13 18:18 ` Samuel Holland 2024-02-13 18:07 ` Conor Dooley 2024-02-13 18:07 ` Conor Dooley 2024-02-13 20:22 ` Samuel Holland 2024-02-13 20:22 ` Samuel Holland 2024-02-13 20:43 ` Stefan O'Rear 2024-02-13 20:43 ` Stefan O'Rear 2024-02-13 23:15 ` Conor Dooley 2024-02-13 23:15 ` Conor Dooley 2024-02-18 15:00 ` Samuel Holland 2024-02-18 15:00 ` Samuel Holland 2024-02-18 17:02 ` Conor Dooley 2024-02-18 17:02 ` Conor Dooley 2024-02-13 3:37 ` [PATCH -fixes v2 4/4] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland 2024-02-13 3:37 ` Samuel Holland 2024-02-13 14:49 ` Andrew Jones 2024-02-13 14:49 ` Andrew Jones 2024-02-13 17:53 ` Stefan O'Rear 2024-02-13 17:53 ` Stefan O'Rear 2024-02-18 14:09 ` Samuel Holland 2024-02-18 14:09 ` Samuel Holland
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