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From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@kernel.org>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Jiancheng Xue <xuejiancheng@hisilicon.com>,
	Alex Elder <elder@linaro.org>,
	 Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, stable@vger.kernel.org,
	 Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
Date: Mon, 19 Feb 2024 23:05:27 +0800	[thread overview]
Message-ID: <20240219-cache-v3-2-a33c57534ae9@outlook.com> (raw)
In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com>

From: Yang Xiwen <forbidden405@outlook.com>

This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index d01023401d7e..fc64d2fa99eb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,11 @@ cpu@3 {
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
-		      <0x0 0xf1002000 0x0 0x2000>;  /* GICC */
+		      <0x0 0xf1002000 0x0 0x2000>,  /* GICC */
+		      <0x0 0xf1004000 0x0 0x2000>,  /* GICH */
+		      <0x0 0xf1006000 0x0 0x2000>;  /* GICV */
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_HIGH)>;
 		#address-cells = <0>;
 		#interrupt-cells = <3>;
 		interrupt-controller;

-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@kernel.org>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Jiancheng Xue <xuejiancheng@hisilicon.com>,
	Alex Elder <elder@linaro.org>,
	 Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, stable@vger.kernel.org,
	 Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
Date: Mon, 19 Feb 2024 23:05:27 +0800	[thread overview]
Message-ID: <20240219-cache-v3-2-a33c57534ae9@outlook.com> (raw)
In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com>

From: Yang Xiwen <forbidden405@outlook.com>

This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index d01023401d7e..fc64d2fa99eb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,11 @@ cpu@3 {
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
-		      <0x0 0xf1002000 0x0 0x2000>;  /* GICC */
+		      <0x0 0xf1002000 0x0 0x2000>,  /* GICC */
+		      <0x0 0xf1004000 0x0 0x2000>,  /* GICH */
+		      <0x0 0xf1006000 0x0 0x2000>;  /* GICV */
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_HIGH)>;
 		#address-cells = <0>;
 		#interrupt-cells = <3>;
 		interrupt-controller;

-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Yang Xiwen <forbidden405@outlook.com>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Jiancheng Xue <xuejiancheng@hisilicon.com>,
	Alex Elder <elder@linaro.org>,
	 Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, stable@vger.kernel.org,
	 Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
Date: Mon, 19 Feb 2024 23:05:27 +0800	[thread overview]
Message-ID: <20240219-cache-v3-2-a33c57534ae9@outlook.com> (raw)
In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com>

This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index d01023401d7e..fc64d2fa99eb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,11 @@ cpu@3 {
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
-		      <0x0 0xf1002000 0x0 0x2000>;  /* GICC */
+		      <0x0 0xf1002000 0x0 0x2000>,  /* GICC */
+		      <0x0 0xf1004000 0x0 0x2000>,  /* GICH */
+		      <0x0 0xf1006000 0x0 0x2000>;  /* GICV */
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+			      IRQ_TYPE_LEVEL_HIGH)>;
 		#address-cells = <0>;
 		#interrupt-cells = <3>;
 		interrupt-controller;

-- 
2.43.0


  parent reply	other threads:[~2024-02-19 15:07 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-19 15:05 [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen via B4 Relay
2024-02-19 15:05 ` Yang Xiwen
2024-02-19 15:05 ` Yang Xiwen via B4 Relay
2024-02-19 15:05 ` [PATCH v3 1/3] arm64: dts: hi3798cv200: fix the size of GICR Yang Xiwen via B4 Relay
2024-02-19 15:05   ` Yang Xiwen
2024-02-19 15:05   ` Yang Xiwen via B4 Relay
2024-02-19 15:05 ` Yang Xiwen via B4 Relay [this message]
2024-02-19 15:05   ` [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Yang Xiwen
2024-02-19 15:05   ` Yang Xiwen via B4 Relay
2024-02-19 15:11   ` kernel test robot
2024-02-19 15:05 ` [PATCH v3 3/3] arm64: dts: hi3798cv200: add cache info Yang Xiwen via B4 Relay
2024-02-19 15:05   ` Yang Xiwen
2024-02-19 15:05   ` Yang Xiwen via B4 Relay
2024-03-12 11:19 ` [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen
2024-03-12 11:19   ` Yang Xiwen
2024-03-12 11:33   ` Wei Xu
2024-03-12 11:33     ` Wei Xu
2024-03-12 11:46     ` Yang Xiwen
2024-03-12 11:46       ` Yang Xiwen
2024-03-12 11:58       ` Wei Xu
2024-03-12 11:58         ` Wei Xu
2024-03-12 11:36   ` Krzysztof Kozlowski
2024-03-12 11:36     ` Krzysztof Kozlowski
2024-03-12 12:00     ` Wei Xu
2024-03-12 12:00       ` Wei Xu
2024-04-08  7:31 ` Krzysztof Kozlowski
2024-04-08  7:31   ` Krzysztof Kozlowski
2024-04-08  8:09   ` Wei Xu
2024-04-08  8:09     ` Wei Xu
2024-04-08  9:09   ` Yang Xiwen
2024-04-08  9:09     ` Yang Xiwen

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