From: Charles Perry <charles.perry@savoirfairelinux.com> To: mdf@kernel.org Cc: avandiver@markem-imaje.com, bcody@markem-imaje.com, Charles Perry <charles.perry@savoirfairelinux.com>, Wu Hao <hao.wu@intel.com>, Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michal Simek <michal.simek@amd.com>, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] dt-bindings: fpga: xlnx,fpga-selectmap: add DT schema Date: Wed, 21 Feb 2024 14:50:48 -0500 [thread overview] Message-ID: <20240221195058.1281973-3-charles.perry@savoirfairelinux.com> (raw) In-Reply-To: <20240221195058.1281973-1-charles.perry@savoirfairelinux.com> Document the SelectMAP interface of Xilinx 7 series FPGA. Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com> --- .../bindings/fpga/xlnx,fpga-selectmap.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml new file mode 100644 index 0000000000000..08a5e92781657 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SelectMAP FPGA interface + +maintainers: + - Charles Perry <charles.perry@savoirfairelinux.com> + +description: | + Xilinx 7 Series FPGAs support a method of loading the bitstream over a + parallel port named the SelectMAP interface in the documentation. Only + the x8 mode is supported where data is loaded at one byte per rising edge of + the clock, with the MSB of each byte presented to the D0 pin. + + Datasheets: + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf + +allOf: + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + +properties: + compatible: + enum: + - xlnx,fpga-xc7s-selectmap + - xlnx,fpga-xc7a-selectmap + - xlnx,fpga-xc7k-selectmap + - xlnx,fpga-xc7v-selectmap + + reg: + description: + At least 1 byte of memory mapped IO + maxItems: 1 + + prog_b-gpios: + description: + config pin (referred to as PROGRAM_B in the manual) + maxItems: 1 + + done-gpios: + description: + config status pin (referred to as DONE in the manual) + maxItems: 1 + + init-b-gpios: + description: + initialization status and configuration error pin + (referred to as INIT_B in the manual) + maxItems: 1 + + csi-gpios: + description: + chip select pin (referred to as CSI_B in the manual) + Optional gpio for if the bus controller does not provide a chip select. + maxItems: 1 + + rdwr-gpios: + description: + read/write select pin (referred to as RDWR_B in the manual) + Optional gpio for if the bus controller does not provide this pin. + maxItems: 1 + +required: + - compatible + - reg + - prog_b-gpios + - done-gpios + - init-b-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + fpga-mgr@8000000 { + compatible = "xlnx,fpga-xc7s-selectmap"; + reg = <0x8000000 0x4>; + prog_b-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + init-b-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + csi-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + rdwr-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; +... -- 2.43.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Charles Perry <charles.perry@savoirfairelinux.com> To: mdf@kernel.org Cc: avandiver@markem-imaje.com, bcody@markem-imaje.com, Charles Perry <charles.perry@savoirfairelinux.com>, Wu Hao <hao.wu@intel.com>, Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michal Simek <michal.simek@amd.com>, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] dt-bindings: fpga: xlnx,fpga-selectmap: add DT schema Date: Wed, 21 Feb 2024 14:50:48 -0500 [thread overview] Message-ID: <20240221195058.1281973-3-charles.perry@savoirfairelinux.com> (raw) In-Reply-To: <20240221195058.1281973-1-charles.perry@savoirfairelinux.com> Document the SelectMAP interface of Xilinx 7 series FPGA. Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com> --- .../bindings/fpga/xlnx,fpga-selectmap.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml new file mode 100644 index 0000000000000..08a5e92781657 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SelectMAP FPGA interface + +maintainers: + - Charles Perry <charles.perry@savoirfairelinux.com> + +description: | + Xilinx 7 Series FPGAs support a method of loading the bitstream over a + parallel port named the SelectMAP interface in the documentation. Only + the x8 mode is supported where data is loaded at one byte per rising edge of + the clock, with the MSB of each byte presented to the D0 pin. + + Datasheets: + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf + +allOf: + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + +properties: + compatible: + enum: + - xlnx,fpga-xc7s-selectmap + - xlnx,fpga-xc7a-selectmap + - xlnx,fpga-xc7k-selectmap + - xlnx,fpga-xc7v-selectmap + + reg: + description: + At least 1 byte of memory mapped IO + maxItems: 1 + + prog_b-gpios: + description: + config pin (referred to as PROGRAM_B in the manual) + maxItems: 1 + + done-gpios: + description: + config status pin (referred to as DONE in the manual) + maxItems: 1 + + init-b-gpios: + description: + initialization status and configuration error pin + (referred to as INIT_B in the manual) + maxItems: 1 + + csi-gpios: + description: + chip select pin (referred to as CSI_B in the manual) + Optional gpio for if the bus controller does not provide a chip select. + maxItems: 1 + + rdwr-gpios: + description: + read/write select pin (referred to as RDWR_B in the manual) + Optional gpio for if the bus controller does not provide this pin. + maxItems: 1 + +required: + - compatible + - reg + - prog_b-gpios + - done-gpios + - init-b-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + fpga-mgr@8000000 { + compatible = "xlnx,fpga-xc7s-selectmap"; + reg = <0x8000000 0x4>; + prog_b-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + init-b-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + csi-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + rdwr-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; +... -- 2.43.0
next prev parent reply other threads:[~2024-02-21 19:52 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-21 19:50 [PATCH v4 0/3] fpga: xilinx-selectmap: add new driver Charles Perry 2024-02-21 19:50 ` Charles Perry 2024-02-21 19:50 ` [PATCH v4 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry 2024-02-21 19:50 ` Charles Perry 2024-02-26 9:19 ` Xu Yilun 2024-02-26 9:19 ` Xu Yilun 2024-03-03 17:20 ` Charles Perry 2024-03-03 17:20 ` Charles Perry 2024-03-01 5:29 ` kernel test robot 2024-03-01 5:29 ` kernel test robot 2024-02-21 19:50 ` Charles Perry [this message] 2024-02-21 19:50 ` [PATCH v4 2/3] dt-bindings: fpga: xlnx,fpga-selectmap: add DT schema Charles Perry 2024-02-27 10:10 ` Krzysztof Kozlowski 2024-02-27 10:10 ` Krzysztof Kozlowski 2024-03-03 17:21 ` Charles Perry 2024-03-03 17:21 ` Charles Perry 2024-03-04 7:30 ` Krzysztof Kozlowski 2024-03-04 7:30 ` Krzysztof Kozlowski 2024-03-04 7:31 ` Krzysztof Kozlowski 2024-03-04 7:31 ` Krzysztof Kozlowski 2024-03-05 2:27 ` Charles Perry 2024-03-05 2:27 ` Charles Perry 2024-03-05 7:27 ` Krzysztof Kozlowski 2024-03-05 7:27 ` Krzysztof Kozlowski 2024-03-06 7:10 ` Xu Yilun 2024-03-06 7:10 ` Xu Yilun 2024-03-06 14:29 ` Charles Perry 2024-03-06 14:29 ` Charles Perry 2024-02-21 19:50 ` [PATCH v4 3/3] fpga: xilinx-selectmap: add new driver Charles Perry 2024-02-21 19:50 ` Charles Perry 2024-02-26 9:50 ` Xu Yilun 2024-02-26 9:50 ` Xu Yilun 2024-03-03 17:22 ` Charles Perry 2024-03-03 17:22 ` Charles Perry 2024-03-13 22:47 ` Charles Perry 2024-03-13 22:47 ` Charles Perry
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