From: Yu Chien Peter Lin <peterlin@andestech.com> To: <acme@kernel.org>, <adrian.hunter@intel.com>, <ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>, <andre.przywara@arm.com>, <anup@brainfault.org>, <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>, <conor+dt@kernel.org>, <conor.dooley@microchip.com>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <evan@rivosinc.com>, <geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>, <irogers@google.com>, <jernej.skrabec@gmail.com>, <jolsa@kernel.org>, <jszhang@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>, <linux-renesas-soc@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>, <locus84@andestech.com>, <magnus.damm@gmail.com>, <mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>, <namhyung@kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <peterlin@andestech.com>, <peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <sunilvl@ventanamicro.com>, <tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>, <will@kernel.org>, <inochiama@outlook.com>, <unicorn_wang@outlook.com>, <wefu@redhat.com> Cc: Randolph <randolph@andestech.com> Subject: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Date: Thu, 22 Feb 2024 16:39:39 +0800 [thread overview] Message-ID: <20240222083946.3977135-4-peterlin@andestech.com> (raw) In-Reply-To: <20240222083946.3977135-1-peterlin@andestech.com> Add support for the Andes hart-level interrupt controller. This controller provides interrupt mask/unmask functions to access the custom register (SLIE) where the non-standard S-mode local interrupt enable bits are located. The base of custom interrupt number is set to 256. To share the riscv_intc_domain_map() with the generic RISC-V INTC and ACPI, add a chip parameter to riscv_intc_init_common(), so it can be passed to the irq_domain_set_info() as a private data. Andes hart-level interrupt controller requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node to enable the use of custom local interrupt source. e.g., cpu0: cpu@0 { compatible = "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells = <0x01>; compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC Changes v3 -> v4: (Suggested by Thomas [1]) - Add comment to andes irq chip function - Refine code flow to share with generic RISC-V INTC and ACPI - Move Andes specific definitions to include/linux/soc/andes/irq.h Changes v4 -> v5: (Suggested by Thomas) - Fix commit message - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask - Do not set chip_data to the chip itself with irq_domain_set_info() - Follow reverse fir tree order variable declarations Changes v5 -> v6: - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI - Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup) - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32) Changes v6 -> v7: - No change Changes v7 -> v8: - Include Reviewed-by tags from Anup Changes v8 -> v9: - No functional change [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/ --- drivers/irqchip/irq-riscv-intc.c | 58 ++++++++++++++++++++++++++++---- include/linux/soc/andes/irq.h | 18 ++++++++++ 2 files changed, 69 insertions(+), 7 deletions(-) create mode 100644 include/linux/soc/andes/irq.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 684875c39728..0cd6b48a5dbf 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/smp.h> +#include <linux/soc/andes/irq.h> static struct irq_domain *intc_domain; static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG; @@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } +static void andes_intc_irq_mask(struct irq_data *d) +{ + /* + * Andes specific S-mode local interrupt causes (hwirq) + * are defined as (256 + n) and controlled by n-th bit + * of SLIE. + */ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip = { .irq_eoi = riscv_intc_irq_eoi, }; +static struct irq_chip andes_intc_chip = { + .name = "RISC-V INTC", + .irq_mask = andes_intc_irq_mask, + .irq_unmask = andes_intc_irq_unmask, + .irq_eoi = riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct irq_chip *chip = d->host_data; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, - handle_percpu_devid_irq, NULL, NULL); + irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, + NULL, NULL); return 0; } @@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } -static int __init riscv_intc_init_common(struct fwnode_handle *fn) +static int __init riscv_intc_init_common(struct fwnode_handle *fn, + struct irq_chip *chip) { int rc; - intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc; + struct irq_chip *chip = &riscv_intc_chip; unsigned long hartid; + int rc; rc = riscv_of_parent_hartid(node, &hartid); if (rc < 0) { @@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node, return 0; } - return riscv_intc_init_common(of_node_to_fwnode(node)); + if (of_device_is_compatible(node, "andestech,cpu-intc")) { + riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE; + riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST; + chip = &andes_intc_chip; + } + + return riscv_intc_init_common(of_node_to_fwnode(node), chip); } IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI @@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, return -ENOMEM; } - return riscv_intc_init_common(fn); + return riscv_intc_init_common(fn, &riscv_intc_chip); } IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h new file mode 100644 index 000000000000..edc3182d6e66 --- /dev/null +++ b/include/linux/soc/andes/irq.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __ANDES_IRQ_H +#define __ANDES_IRQ_H + +/* Andes PMU irq number */ +#define ANDES_RV_IRQ_PMOVI 18 +#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI +#define ANDES_SLI_CAUSE_BASE 256 + +/* Andes PMU related registers */ +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 +#define ANDES_CSR_SCOUNTEROF 0x9d4 + +#endif /* __ANDES_IRQ_H */ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Yu Chien Peter Lin <peterlin@andestech.com> To: <acme@kernel.org>, <adrian.hunter@intel.com>, <ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>, <andre.przywara@arm.com>, <anup@brainfault.org>, <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>, <conor+dt@kernel.org>, <conor.dooley@microchip.com>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <evan@rivosinc.com>, <geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>, <irogers@google.com>, <jernej.skrabec@gmail.com>, <jolsa@kernel.org>, <jszhang@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>, <linux-renesas-soc@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>, <locus84@andestech.com>, <magnus.damm@gmail.com>, <mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>, <namhyung@kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <peterlin@andestech.com>, <peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <sunilvl@ventanamicro.com>, <tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>, <will@kernel.org>, <inochiama@outlook.com>, <unicorn_wang@outlook.com>, <wefu@redhat.com> Cc: Randolph <randolph@andestech.com> Subject: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Date: Thu, 22 Feb 2024 16:39:39 +0800 [thread overview] Message-ID: <20240222083946.3977135-4-peterlin@andestech.com> (raw) In-Reply-To: <20240222083946.3977135-1-peterlin@andestech.com> Add support for the Andes hart-level interrupt controller. This controller provides interrupt mask/unmask functions to access the custom register (SLIE) where the non-standard S-mode local interrupt enable bits are located. The base of custom interrupt number is set to 256. To share the riscv_intc_domain_map() with the generic RISC-V INTC and ACPI, add a chip parameter to riscv_intc_init_common(), so it can be passed to the irq_domain_set_info() as a private data. Andes hart-level interrupt controller requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node to enable the use of custom local interrupt source. e.g., cpu0: cpu@0 { compatible = "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells = <0x01>; compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC Changes v3 -> v4: (Suggested by Thomas [1]) - Add comment to andes irq chip function - Refine code flow to share with generic RISC-V INTC and ACPI - Move Andes specific definitions to include/linux/soc/andes/irq.h Changes v4 -> v5: (Suggested by Thomas) - Fix commit message - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask - Do not set chip_data to the chip itself with irq_domain_set_info() - Follow reverse fir tree order variable declarations Changes v5 -> v6: - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI - Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup) - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32) Changes v6 -> v7: - No change Changes v7 -> v8: - Include Reviewed-by tags from Anup Changes v8 -> v9: - No functional change [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/ --- drivers/irqchip/irq-riscv-intc.c | 58 ++++++++++++++++++++++++++++---- include/linux/soc/andes/irq.h | 18 ++++++++++ 2 files changed, 69 insertions(+), 7 deletions(-) create mode 100644 include/linux/soc/andes/irq.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 684875c39728..0cd6b48a5dbf 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/smp.h> +#include <linux/soc/andes/irq.h> static struct irq_domain *intc_domain; static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG; @@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } +static void andes_intc_irq_mask(struct irq_data *d) +{ + /* + * Andes specific S-mode local interrupt causes (hwirq) + * are defined as (256 + n) and controlled by n-th bit + * of SLIE. + */ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip = { .irq_eoi = riscv_intc_irq_eoi, }; +static struct irq_chip andes_intc_chip = { + .name = "RISC-V INTC", + .irq_mask = andes_intc_irq_mask, + .irq_unmask = andes_intc_irq_unmask, + .irq_eoi = riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct irq_chip *chip = d->host_data; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, - handle_percpu_devid_irq, NULL, NULL); + irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, + NULL, NULL); return 0; } @@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } -static int __init riscv_intc_init_common(struct fwnode_handle *fn) +static int __init riscv_intc_init_common(struct fwnode_handle *fn, + struct irq_chip *chip) { int rc; - intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc; + struct irq_chip *chip = &riscv_intc_chip; unsigned long hartid; + int rc; rc = riscv_of_parent_hartid(node, &hartid); if (rc < 0) { @@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node, return 0; } - return riscv_intc_init_common(of_node_to_fwnode(node)); + if (of_device_is_compatible(node, "andestech,cpu-intc")) { + riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE; + riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST; + chip = &andes_intc_chip; + } + + return riscv_intc_init_common(of_node_to_fwnode(node), chip); } IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI @@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, return -ENOMEM; } - return riscv_intc_init_common(fn); + return riscv_intc_init_common(fn, &riscv_intc_chip); } IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h new file mode 100644 index 000000000000..edc3182d6e66 --- /dev/null +++ b/include/linux/soc/andes/irq.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __ANDES_IRQ_H +#define __ANDES_IRQ_H + +/* Andes PMU irq number */ +#define ANDES_RV_IRQ_PMOVI 18 +#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI +#define ANDES_SLI_CAUSE_BASE 256 + +/* Andes PMU related registers */ +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 +#define ANDES_CSR_SCOUNTEROF 0x9d4 + +#endif /* __ANDES_IRQ_H */ -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-02-22 8:41 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 21:33 ` Thomas Gleixner 2024-02-22 21:33 ` Thomas Gleixner 2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin [this message] 2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin 2024-02-22 21:36 ` Thomas Gleixner 2024-02-22 21:36 ` Thomas Gleixner 2024-02-23 8:49 ` Thomas Gleixner 2024-02-23 8:49 ` Thomas Gleixner 2024-02-23 8:54 ` Thomas Gleixner 2024-02-23 8:54 ` Thomas Gleixner 2024-02-23 9:06 ` Thomas Gleixner 2024-02-23 9:06 ` Thomas Gleixner 2024-03-12 14:23 ` Palmer Dabbelt 2024-03-12 14:23 ` Palmer Dabbelt 2024-03-12 14:28 ` Thomas Gleixner 2024-03-12 14:28 ` Thomas Gleixner 2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-26 12:27 ` Geert Uytterhoeven 2024-02-26 12:27 ` Geert Uytterhoeven 2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-26 12:28 ` Geert Uytterhoeven 2024-02-26 12:28 ` Geert Uytterhoeven 2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv 2024-03-14 12:30 ` patchwork-bot+linux-riscv
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20240222083946.3977135-4-peterlin@andestech.com \ --to=peterlin@andestech.com \ --cc=acme@kernel.org \ --cc=adrian.hunter@intel.com \ --cc=ajones@ventanamicro.com \ --cc=alexander.shishkin@linux.intel.com \ --cc=andre.przywara@arm.com \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=atishp@atishpatra.org \ --cc=conor+dt@kernel.org \ --cc=conor.dooley@microchip.com \ --cc=conor@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=evan@rivosinc.com \ --cc=geert+renesas@glider.be \ --cc=guoren@kernel.org \ --cc=heiko@sntech.de \ --cc=inochiama@outlook.com \ --cc=irogers@google.com \ --cc=jernej.skrabec@gmail.com \ --cc=jolsa@kernel.org \ --cc=jszhang@kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-perf-users@vger.kernel.org \ --cc=linux-renesas-soc@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=linux-sunxi@lists.linux.dev \ --cc=locus84@andestech.com \ --cc=magnus.damm@gmail.com \ --cc=mark.rutland@arm.com \ --cc=mingo@redhat.com \ --cc=n.shubin@yadro.com \ --cc=namhyung@kernel.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=peterz@infradead.org \ --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \ --cc=randolph@andestech.com \ --cc=rdunlap@infradead.org \ --cc=robh+dt@kernel.org \ --cc=samuel@sholland.org \ --cc=sunilvl@ventanamicro.com \ --cc=tglx@linutronix.de \ --cc=tim609@andestech.com \ --cc=unicorn_wang@outlook.com \ --cc=uwu@icenowy.me \ --cc=wefu@redhat.com \ --cc=wens@csie.org \ --cc=will@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.