From: Yu Chien Peter Lin <peterlin@andestech.com> To: <acme@kernel.org>, <adrian.hunter@intel.com>, <ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>, <andre.przywara@arm.com>, <anup@brainfault.org>, <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>, <conor+dt@kernel.org>, <conor.dooley@microchip.com>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <evan@rivosinc.com>, <geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>, <irogers@google.com>, <jernej.skrabec@gmail.com>, <jolsa@kernel.org>, <jszhang@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>, <linux-renesas-soc@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>, <locus84@andestech.com>, <magnus.damm@gmail.com>, <mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>, <namhyung@kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <peterlin@andestech.com>, <peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <sunilvl@ventanamicro.com>, <tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>, <will@kernel.org>, <inochiama@outlook.com>, <unicorn_wang@outlook.com>, <wefu@redhat.com> Cc: Atish Patra <atishp@rivosinc.com> Subject: [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Date: Thu, 22 Feb 2024 16:39:42 +0800 [thread overview] Message-ID: <20240222083946.3977135-7-peterlin@andestech.com> (raw) In-Reply-To: <20240222083946.3977135-1-peterlin@andestech.com> The interrupt enable/disable operations are already performed by the IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during enable_percpu_irq()/disable_percpu_irq(). It can be done only once. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE} in the initial PATCH3 [1]. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/ Changes v1 -> v2: - New patch Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - No change Changes v5 -> v6: - No change Changes v6 -> v7: - No change Changes v7 -> v8: - Include Reviewed-by tags from Atish Changes v8 -> v9: - No change --- drivers/perf/riscv_pmu_sbi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..2edbc37abadf 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); - csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } @@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); - csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); } /* Disable all counters access for user mode now */ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Yu Chien Peter Lin <peterlin@andestech.com> To: <acme@kernel.org>, <adrian.hunter@intel.com>, <ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>, <andre.przywara@arm.com>, <anup@brainfault.org>, <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>, <conor+dt@kernel.org>, <conor.dooley@microchip.com>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <evan@rivosinc.com>, <geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>, <irogers@google.com>, <jernej.skrabec@gmail.com>, <jolsa@kernel.org>, <jszhang@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>, <linux-renesas-soc@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>, <locus84@andestech.com>, <magnus.damm@gmail.com>, <mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>, <namhyung@kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <peterlin@andestech.com>, <peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <sunilvl@ventanamicro.com>, <tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>, <will@kernel.org>, <inochiama@outlook.com>, <unicorn_wang@outlook.com>, <wefu@redhat.com> Cc: Atish Patra <atishp@rivosinc.com> Subject: [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Date: Thu, 22 Feb 2024 16:39:42 +0800 [thread overview] Message-ID: <20240222083946.3977135-7-peterlin@andestech.com> (raw) In-Reply-To: <20240222083946.3977135-1-peterlin@andestech.com> The interrupt enable/disable operations are already performed by the IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during enable_percpu_irq()/disable_percpu_irq(). It can be done only once. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE} in the initial PATCH3 [1]. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/ Changes v1 -> v2: - New patch Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - No change Changes v5 -> v6: - No change Changes v6 -> v7: - No change Changes v7 -> v8: - Include Reviewed-by tags from Atish Changes v8 -> v9: - No change --- drivers/perf/riscv_pmu_sbi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..2edbc37abadf 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); - csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } @@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); - csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); } /* Disable all counters access for user mode now */ -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-02-22 8:41 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 21:33 ` Thomas Gleixner 2024-02-22 21:33 ` Thomas Gleixner 2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 21:36 ` Thomas Gleixner 2024-02-22 21:36 ` Thomas Gleixner 2024-02-23 8:49 ` Thomas Gleixner 2024-02-23 8:49 ` Thomas Gleixner 2024-02-23 8:54 ` Thomas Gleixner 2024-02-23 8:54 ` Thomas Gleixner 2024-02-23 9:06 ` Thomas Gleixner 2024-02-23 9:06 ` Thomas Gleixner 2024-03-12 14:23 ` Palmer Dabbelt 2024-03-12 14:23 ` Palmer Dabbelt 2024-03-12 14:28 ` Thomas Gleixner 2024-03-12 14:28 ` Thomas Gleixner 2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-26 12:27 ` Geert Uytterhoeven 2024-02-26 12:27 ` Geert Uytterhoeven 2024-02-22 8:39 ` Yu Chien Peter Lin [this message] 2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-02-26 12:28 ` Geert Uytterhoeven 2024-02-26 12:28 ` Geert Uytterhoeven 2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin 2024-02-22 8:39 ` Yu Chien Peter Lin 2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv 2024-03-14 12:30 ` patchwork-bot+linux-riscv
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