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From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>
Cc: David Yang <mmyangfl@gmail.com>,
	 Igor Opaniuk <igor.opaniuk@foundries.io>,
	 Jorge Ramirez-Ortiz Gmail <jorge.ramirez.ortiz@gmail.com>,
	 linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function
Date: Sun, 25 Feb 2024 00:56:09 +0800	[thread overview]
Message-ID: <20240225-pll-v1-1-fad6511479c6@outlook.com> (raw)
In-Reply-To: <20240225-pll-v1-0-fad6511479c6@outlook.com>

From: Yang Xiwen <forbidden405@outlook.com>

Hi3559 clock drivers implemented their own PLL driver. Unfortunately
our generic PLL driver will use a same name. So add a prefix "_" to
avoid that.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
 drivers/clk/hisilicon/clk-hi3559a.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
index ff4ca0edce06..77fa4203a428 100644
--- a/drivers/clk/hisilicon/clk-hi3559a.c
+++ b/drivers/clk/hisilicon/clk-hi3559a.c
@@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 };
 
-static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
+static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
 			   int nums, struct hisi_clock_data *data, struct device *dev)
 {
 	void __iomem *base = data->base;
@@ -517,7 +517,7 @@ static struct hisi_clock_data *hi3559av100_clk_register(
 	if (ret)
 		return ERR_PTR(ret);
 
-	hisi_clk_register_pll(hi3559av100_pll_clks,
+	_hisi_clk_register_pll(hi3559av100_pll_clks,
 			      ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);
 
 	ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,

-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: Yang Xiwen <forbidden405@outlook.com>
To: Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>
Cc: David Yang <mmyangfl@gmail.com>,
	 Igor Opaniuk <igor.opaniuk@foundries.io>,
	 Jorge Ramirez-Ortiz Gmail <jorge.ramirez.ortiz@gmail.com>,
	 linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function
Date: Sun, 25 Feb 2024 00:56:09 +0800	[thread overview]
Message-ID: <20240225-pll-v1-1-fad6511479c6@outlook.com> (raw)
In-Reply-To: <20240225-pll-v1-0-fad6511479c6@outlook.com>

Hi3559 clock drivers implemented their own PLL driver. Unfortunately
our generic PLL driver will use a same name. So add a prefix "_" to
avoid that.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
 drivers/clk/hisilicon/clk-hi3559a.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
index ff4ca0edce06..77fa4203a428 100644
--- a/drivers/clk/hisilicon/clk-hi3559a.c
+++ b/drivers/clk/hisilicon/clk-hi3559a.c
@@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 };
 
-static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
+static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
 			   int nums, struct hisi_clock_data *data, struct device *dev)
 {
 	void __iomem *base = data->base;
@@ -517,7 +517,7 @@ static struct hisi_clock_data *hi3559av100_clk_register(
 	if (ret)
 		return ERR_PTR(ret);
 
-	hisi_clk_register_pll(hi3559av100_pll_clks,
+	_hisi_clk_register_pll(hi3559av100_pll_clks,
 			      ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);
 
 	ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,

-- 
2.43.0


  reply	other threads:[~2024-02-24 16:56 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-24 16:56 [PATCH RFC 0/2] clk: hisilicon: add support for PLL Yang Xiwen via B4 Relay
2024-02-24 16:56 ` Yang Xiwen
2024-02-24 16:56 ` Yang Xiwen via B4 Relay [this message]
2024-02-24 16:56   ` [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function Yang Xiwen
2024-04-11  6:52   ` Stephen Boyd
2024-04-11  7:44     ` Yang Xiwen
2024-04-11  7:53       ` Stephen Boyd
2024-04-11 10:31         ` Yang Xiwen
2024-04-12  3:03           ` Stephen Boyd
2024-02-24 16:56 ` [PATCH RFC 2/2] clk: hisilicon: add support for PLL Yang Xiwen via B4 Relay
2024-02-24 16:56   ` Yang Xiwen
2024-02-27  3:06   ` kernel test robot
2024-04-11  6:59   ` Stephen Boyd
2024-04-11  7:54     ` Yang Xiwen

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