From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com> Cc: Andrew Jones <ajones@ventanamicro.com>, linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>, linux-riscv@lists.infradead.org, Stefan O'Rear <sorear@fastmail.com>, Samuel Holland <samuel.holland@sifive.com>, stable@vger.kernel.org Subject: [PATCH -fixes v4 3/3] riscv: Save/restore envcfg CSR during CPU suspend Date: Tue, 27 Feb 2024 22:55:35 -0800 [thread overview] Message-ID: <20240228065559.3434837-4-samuel.holland@sifive.com> (raw) In-Reply-To: <20240228065559.3434837-1-samuel.holland@sifive.com> The value of the [ms]envcfg CSR is lost when entering a nonretentive idle state, so the CSR must be rewritten when resuming the CPU. Cc: <stable@vger.kernel.org> # v6.7+ Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v4: - Check for Xlinuxenvcfg instead of Zicboz Changes in v3: - Check for Zicboz instead of the privileged ISA version Changes in v2: - Check for privileged ISA v1.12 instead of the specific CSR - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/suspend.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..299795341e8a 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,8 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) + context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) + csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie); -- 2.43.1
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com> Cc: Andrew Jones <ajones@ventanamicro.com>, linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>, linux-riscv@lists.infradead.org, Stefan O'Rear <sorear@fastmail.com>, Samuel Holland <samuel.holland@sifive.com>, stable@vger.kernel.org Subject: [PATCH -fixes v4 3/3] riscv: Save/restore envcfg CSR during CPU suspend Date: Tue, 27 Feb 2024 22:55:35 -0800 [thread overview] Message-ID: <20240228065559.3434837-4-samuel.holland@sifive.com> (raw) In-Reply-To: <20240228065559.3434837-1-samuel.holland@sifive.com> The value of the [ms]envcfg CSR is lost when entering a nonretentive idle state, so the CSR must be rewritten when resuming the CPU. Cc: <stable@vger.kernel.org> # v6.7+ Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v4: - Check for Xlinuxenvcfg instead of Zicboz Changes in v3: - Check for Zicboz instead of the privileged ISA version Changes in v2: - Check for privileged ISA v1.12 instead of the specific CSR - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/suspend.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..299795341e8a 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,8 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) + context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) + csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie); -- 2.43.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-02-28 6:56 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-28 6:55 [PATCH -fixes v4 0/3] riscv: cbo.zero fixes Samuel Holland 2024-02-28 6:55 ` Samuel Holland 2024-02-28 6:55 ` [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland 2024-02-28 6:55 ` Samuel Holland 2024-02-28 10:13 ` Conor Dooley 2024-02-28 10:13 ` Conor Dooley 2024-02-28 6:55 ` [PATCH -fixes v4 2/3] riscv: Add a custom ISA extension for the [ms]envcfg CSR Samuel Holland 2024-02-28 6:55 ` Samuel Holland 2024-02-28 10:12 ` Conor Dooley 2024-02-28 10:12 ` Conor Dooley 2024-02-29 18:23 ` Palmer Dabbelt 2024-02-29 18:23 ` Palmer Dabbelt 2024-02-29 18:30 ` Conor Dooley 2024-02-29 18:30 ` Conor Dooley 2024-02-29 23:40 ` Palmer Dabbelt 2024-02-29 23:40 ` Palmer Dabbelt 2024-02-28 13:23 ` Andrew Jones 2024-02-28 13:23 ` Andrew Jones 2024-02-28 6:55 ` Samuel Holland [this message] 2024-02-28 6:55 ` [PATCH -fixes v4 3/3] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland 2024-02-28 10:14 ` Conor Dooley 2024-02-28 10:14 ` Conor Dooley 2024-02-28 13:27 ` Andrew Jones 2024-02-28 13:27 ` Andrew Jones 2024-02-29 22:10 ` [PATCH -fixes v4 0/3] riscv: cbo.zero fixes patchwork-bot+linux-riscv 2024-02-29 22:10 ` patchwork-bot+linux-riscv
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