From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Icenowy Zheng <uwu@icenowy.me>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, Will Deacon <will@kernel.org> Subject: [PATCH v4 01/15] RISC-V: Fix the typo in Scountovf CSR name Date: Wed, 28 Feb 2024 17:01:16 -0800 [thread overview] Message-ID: <20240229010130.1380926-2-atishp@rivosinc.com> (raw) In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/csr.h | 2 +- arch/riscv/include/asm/errata_list.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..603e5a3c61f9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index ea33288f8a25..cd49eb025ddf 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -114,7 +114,7 @@ asm volatile(ALTERNATIVE( \ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU) \ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, linux-kselftest@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, kvm@vger.kernel.org, Will Deacon <will@kernel.org>, Anup Patel <anup@brainfault.org>, Paul Walmsley <paul.walmsley@sifive.com>, Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Paolo Bonzini <pbonzini@redhat.com>, Guo Ren <guoren@kernel.org>, kvm-riscv@lists.infradead.org, Atish Patra <atishp@atishpatra.org>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, Shuah Khan <shuah@kernel.org>, Andrew Jones <ajones@ventanamicro.com> Subject: [PATCH v4 01/15] RISC-V: Fix the typo in Scountovf CSR name Date: Wed, 28 Feb 2024 17:01:16 -0800 [thread overview] Message-ID: <20240229010130.1380926-2-atishp@rivosinc.com> (raw) In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/csr.h | 2 +- arch/riscv/include/asm/errata_list.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..603e5a3c61f9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index ea33288f8a25..cd49eb025ddf 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -114,7 +114,7 @@ asm volatile(ALTERNATIVE( \ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU) \ -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-02-29 1:01 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-29 1:01 [PATCH v4 00/15] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-02-29 1:01 ` Atish Patra [this message] 2024-02-29 1:01 ` [PATCH v4 01/15] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-03-01 8:25 ` Clément Léger 2024-03-01 8:25 ` Clément Léger 2024-02-29 1:01 ` [PATCH v4 02/15] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 8:27 ` Clément Léger 2024-03-01 8:27 ` Clément Léger 2024-02-29 1:01 ` [PATCH v4 03/15] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 9:52 ` Andrew Jones 2024-03-01 9:52 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 04/15] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 11:14 ` Andrew Jones 2024-03-01 11:14 ` Andrew Jones 2024-03-01 19:30 ` Atish Kumar Patra 2024-03-01 19:30 ` Atish Kumar Patra 2024-02-29 1:01 ` [PATCH v4 05/15] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 14:40 ` Andrew Jones 2024-03-01 14:40 ` Andrew Jones 2024-03-01 15:55 ` Alexandre Ghiti 2024-03-01 15:55 ` Alexandre Ghiti 2024-02-29 1:01 ` [PATCH v4 06/15] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 7:47 ` Andrew Jones 2024-03-02 7:47 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 07/15] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 8:15 ` Andrew Jones 2024-03-02 8:15 ` Andrew Jones 2024-04-01 22:37 ` Atish Patra 2024-04-01 22:37 ` Atish Patra 2024-04-04 12:16 ` Andrew Jones 2024-04-04 12:16 ` Andrew Jones 2024-04-10 22:44 ` Atish Patra 2024-04-10 22:44 ` Atish Patra 2024-04-11 7:38 ` Andrew Jones 2024-04-11 7:38 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 9:49 ` Andrew Jones 2024-03-02 9:49 ` Andrew Jones 2024-04-01 22:36 ` Atish Patra 2024-04-01 22:36 ` Atish Patra 2024-04-03 7:36 ` Atish Patra 2024-04-03 7:36 ` Atish Patra 2024-04-04 13:19 ` Andrew Jones 2024-04-04 13:19 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 09/15] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 10:33 ` Andrew Jones 2024-03-02 10:33 ` Andrew Jones 2024-04-02 8:33 ` Atish Patra 2024-04-02 8:33 ` Atish Patra 2024-04-05 12:05 ` Andrew Jones 2024-04-05 12:05 ` Andrew Jones 2024-04-10 0:11 ` Atish Patra 2024-04-10 0:11 ` Atish Patra 2024-04-10 7:20 ` Andrew Jones 2024-04-10 7:20 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 10/15] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 10:52 ` Andrew Jones 2024-03-02 10:52 ` Andrew Jones 2024-04-02 0:03 ` Atish Patra 2024-04-02 0:03 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 11/15] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:42 ` Anup Patel 2024-03-01 4:42 ` Anup Patel 2024-03-02 10:52 ` Andrew Jones 2024-03-02 10:52 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 12/15] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:43 ` Anup Patel 2024-03-01 4:43 ` Anup Patel 2024-03-02 11:00 ` Andrew Jones 2024-03-02 11:00 ` Andrew Jones 2024-04-02 8:43 ` Atish Patra 2024-04-02 8:43 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 13/15] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:47 ` Anup Patel 2024-03-01 4:47 ` Anup Patel 2024-03-02 1:01 ` Atish Kumar Patra 2024-03-02 1:01 ` Atish Kumar Patra 2024-03-02 11:52 ` Andrew Jones 2024-03-02 11:52 ` Andrew Jones 2024-04-02 8:34 ` Atish Patra 2024-04-02 8:34 ` Atish Patra 2024-04-05 12:48 ` Andrew Jones 2024-04-05 12:48 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 14/15] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:50 ` Anup Patel 2024-03-01 4:50 ` Anup Patel 2024-03-02 12:13 ` Andrew Jones 2024-03-02 12:13 ` Andrew Jones 2024-04-02 8:35 ` Atish Patra 2024-04-02 8:35 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 15/15] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:53 ` Anup Patel 2024-03-01 4:53 ` Anup Patel 2024-03-02 12:35 ` Andrew Jones 2024-03-02 12:35 ` Andrew Jones 2024-04-02 8:42 ` Atish Patra 2024-04-02 8:42 ` Atish Patra
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