From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Anup Patel <anup@brainfault.org>, Palmer Dabbelt <palmer@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Icenowy Zheng <uwu@icenowy.me>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, Will Deacon <will@kernel.org> Subject: [PATCH v4 04/15] RISC-V: Add SBI PMU snapshot definitions Date: Wed, 28 Feb 2024 17:01:19 -0800 [thread overview] Message-ID: <20240229010130.1380926-5-atishp@rivosinc.com> (raw) In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..dfa830f7d54b 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT BIT(1) /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 extern unsigned long sbi_spec_version; struct sbiret { -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, linux-kselftest@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, kvm@vger.kernel.org, Will Deacon <will@kernel.org>, Anup Patel <anup@brainfault.org>, Paul Walmsley <paul.walmsley@sifive.com>, Atish Patra <atishp@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Paolo Bonzini <pbonzini@redhat.com>, Guo Ren <guoren@kernel.org>, kvm-riscv@lists.infradead.org, Atish Patra <atishp@atishpatra.org>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, Shuah Khan <shuah@kernel.org>, Andrew Jones <ajones@ventanamicro.com> Subject: [PATCH v4 04/15] RISC-V: Add SBI PMU snapshot definitions Date: Wed, 28 Feb 2024 17:01:19 -0800 [thread overview] Message-ID: <20240229010130.1380926-5-atishp@rivosinc.com> (raw) In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..dfa830f7d54b 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT BIT(1) /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 extern unsigned long sbi_spec_version; struct sbiret { -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-02-29 1:01 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-29 1:01 [PATCH v4 00/15] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 01/15] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 8:25 ` Clément Léger 2024-03-01 8:25 ` Clément Léger 2024-02-29 1:01 ` [PATCH v4 02/15] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 8:27 ` Clément Léger 2024-03-01 8:27 ` Clément Léger 2024-02-29 1:01 ` [PATCH v4 03/15] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 9:52 ` Andrew Jones 2024-03-01 9:52 ` Andrew Jones 2024-02-29 1:01 ` Atish Patra [this message] 2024-02-29 1:01 ` [PATCH v4 04/15] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-03-01 11:14 ` Andrew Jones 2024-03-01 11:14 ` Andrew Jones 2024-03-01 19:30 ` Atish Kumar Patra 2024-03-01 19:30 ` Atish Kumar Patra 2024-02-29 1:01 ` [PATCH v4 05/15] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 14:40 ` Andrew Jones 2024-03-01 14:40 ` Andrew Jones 2024-03-01 15:55 ` Alexandre Ghiti 2024-03-01 15:55 ` Alexandre Ghiti 2024-02-29 1:01 ` [PATCH v4 06/15] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 7:47 ` Andrew Jones 2024-03-02 7:47 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 07/15] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 8:15 ` Andrew Jones 2024-03-02 8:15 ` Andrew Jones 2024-04-01 22:37 ` Atish Patra 2024-04-01 22:37 ` Atish Patra 2024-04-04 12:16 ` Andrew Jones 2024-04-04 12:16 ` Andrew Jones 2024-04-10 22:44 ` Atish Patra 2024-04-10 22:44 ` Atish Patra 2024-04-11 7:38 ` Andrew Jones 2024-04-11 7:38 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 9:49 ` Andrew Jones 2024-03-02 9:49 ` Andrew Jones 2024-04-01 22:36 ` Atish Patra 2024-04-01 22:36 ` Atish Patra 2024-04-03 7:36 ` Atish Patra 2024-04-03 7:36 ` Atish Patra 2024-04-04 13:19 ` Andrew Jones 2024-04-04 13:19 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 09/15] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 10:33 ` Andrew Jones 2024-03-02 10:33 ` Andrew Jones 2024-04-02 8:33 ` Atish Patra 2024-04-02 8:33 ` Atish Patra 2024-04-05 12:05 ` Andrew Jones 2024-04-05 12:05 ` Andrew Jones 2024-04-10 0:11 ` Atish Patra 2024-04-10 0:11 ` Atish Patra 2024-04-10 7:20 ` Andrew Jones 2024-04-10 7:20 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 10/15] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-02 10:52 ` Andrew Jones 2024-03-02 10:52 ` Andrew Jones 2024-04-02 0:03 ` Atish Patra 2024-04-02 0:03 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 11/15] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:42 ` Anup Patel 2024-03-01 4:42 ` Anup Patel 2024-03-02 10:52 ` Andrew Jones 2024-03-02 10:52 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 12/15] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:43 ` Anup Patel 2024-03-01 4:43 ` Anup Patel 2024-03-02 11:00 ` Andrew Jones 2024-03-02 11:00 ` Andrew Jones 2024-04-02 8:43 ` Atish Patra 2024-04-02 8:43 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 13/15] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:47 ` Anup Patel 2024-03-01 4:47 ` Anup Patel 2024-03-02 1:01 ` Atish Kumar Patra 2024-03-02 1:01 ` Atish Kumar Patra 2024-03-02 11:52 ` Andrew Jones 2024-03-02 11:52 ` Andrew Jones 2024-04-02 8:34 ` Atish Patra 2024-04-02 8:34 ` Atish Patra 2024-04-05 12:48 ` Andrew Jones 2024-04-05 12:48 ` Andrew Jones 2024-02-29 1:01 ` [PATCH v4 14/15] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:50 ` Anup Patel 2024-03-01 4:50 ` Anup Patel 2024-03-02 12:13 ` Andrew Jones 2024-03-02 12:13 ` Andrew Jones 2024-04-02 8:35 ` Atish Patra 2024-04-02 8:35 ` Atish Patra 2024-02-29 1:01 ` [PATCH v4 15/15] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-02-29 1:01 ` Atish Patra 2024-03-01 4:53 ` Anup Patel 2024-03-01 4:53 ` Anup Patel 2024-03-02 12:35 ` Andrew Jones 2024-03-02 12:35 ` Andrew Jones 2024-04-02 8:42 ` Atish Patra 2024-04-02 8:42 ` Atish Patra
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