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From: zan@falconsigh.net
To: dri-devel@lists.freedesktop.org
Cc: freedreno@lists.freedesktop.org, robdclark@gmail.com,
	Zan Dobersek <zdobersek@igalia.com>
Subject: [PATCH] drm/msm/a7xx: allow writing to CP_BV counter selection registers
Date: Thu, 29 Feb 2024 08:49:11 +0100	[thread overview]
Message-ID: <20240229074913.3463365-1-zan@falconsigh.net> (raw)

From: Zan Dobersek <zdobersek@igalia.com>

In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the
CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling
purposes of tools like fdperf and perfetto.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index c9c55e2ea584..09c554f2fcf6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1175,8 +1175,9 @@ static const u32 a730_protect[] = {
 	A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
 	A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
 	A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
-	/* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
-	A6XX_PROTECT_RDONLY(0x008de, 0x0154),
+	/* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
+	A6XX_PROTECT_NORDWR(0x008de, 0x0001),
+	A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
 	A6XX_PROTECT_NORDWR(0x00900, 0x004d),
 	A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
 	A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
-- 
2.43.0


                 reply	other threads:[~2024-02-29  8:03 UTC|newest]

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