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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: [PATCH 2/8] target/arm: Timer _EL02 registers UNDEF for E2H == 0
Date: Fri,  1 Mar 2024 18:32:13 +0000	[thread overview]
Message-ID: <20240301183219.2424889-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org>

The timer _EL02 registers should UNDEF for invalid accesses from EL2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap.  We were
delivering the exception to EL2 with the wrong syndrome.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 90c4fb72ce4..978df6f2823 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6551,7 +6551,7 @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
         return CP_ACCESS_OK;
     }
     if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
-        return CP_ACCESS_TRAP;
+        return CP_ACCESS_TRAP_UNCATEGORIZED;
     }
     return CP_ACCESS_OK;
 }
-- 
2.34.1



  parent reply	other threads:[~2024-03-01 18:34 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-01 18:32 [PATCH 0/8] target/arm: Implement FEAT_ECV (Enhanced Counter Virtualization) Peter Maydell
2024-03-01 18:32 ` [PATCH 1/8] target/arm: Move some register related defines to internals.h Peter Maydell
2024-03-01 19:03   ` Philippe Mathieu-Daudé
2024-03-01 21:01   ` Richard Henderson
2024-03-01 18:32 ` Peter Maydell [this message]
2024-03-01 21:08   ` [PATCH 2/8] target/arm: Timer _EL02 registers UNDEF for E2H == 0 Richard Henderson
2024-03-01 18:32 ` [PATCH 3/8] target/arm: use FIELD macro for CNTHCTL bit definitions Peter Maydell
2024-03-01 19:04   ` Philippe Mathieu-Daudé
2024-03-01 21:10   ` Richard Henderson
2024-03-01 21:19   ` Richard Henderson
2024-03-04 13:21     ` Peter Maydell
2024-03-04 17:02       ` Richard Henderson
2024-03-01 18:32 ` [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Peter Maydell
2024-03-01 21:11   ` Richard Henderson
2024-03-01 18:32 ` [PATCH 5/8] target/arm: Implement new FEAT_ECV trap bits Peter Maydell
2024-03-01 21:37   ` Richard Henderson
2024-03-01 18:32 ` [PATCH 6/8] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 Peter Maydell
2024-03-01 21:41   ` Richard Henderson
2024-03-01 18:32 ` [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling Peter Maydell
2024-03-01 21:54   ` Richard Henderson
2024-03-02 10:59     ` Peter Maydell
2024-03-01 18:32 ` [PATCH 8/8] target/arm: Enable FEAT_ECV for 'max' CPU Peter Maydell
2024-03-01 19:05   ` Philippe Mathieu-Daudé
2024-03-01 21:58   ` Richard Henderson

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