From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: [PATCH 8/8] target/arm: Enable FEAT_ECV for 'max' CPU
Date: Fri, 1 Mar 2024 18:32:19 +0000 [thread overview]
Message-ID: <20240301183219.2424889-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20240301183219.2424889-1-peter.maydell@linaro.org>
Enable all FEAT_ECV features on the 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index f67aea2d836..2a7bbb82dc4 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -28,6 +28,7 @@ the following architecture extensions:
- FEAT_DotProd (Advanced SIMD dot product instructions)
- FEAT_DoubleFault (Double Fault Extension)
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
+- FEAT_ECV (Enhanced Counter Virtualization)
- FEAT_EPAC (Enhanced pointer authentication)
- FEAT_ETS (Enhanced Translation Synchronization)
- FEAT_EVT (Enhanced Virtualization Traps)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 5fba2c0f040..9f7a9f3d2cc 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1184,6 +1184,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
--
2.34.1
next prev parent reply other threads:[~2024-03-01 18:33 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-01 18:32 [PATCH 0/8] target/arm: Implement FEAT_ECV (Enhanced Counter Virtualization) Peter Maydell
2024-03-01 18:32 ` [PATCH 1/8] target/arm: Move some register related defines to internals.h Peter Maydell
2024-03-01 19:03 ` Philippe Mathieu-Daudé
2024-03-01 21:01 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 2/8] target/arm: Timer _EL02 registers UNDEF for E2H == 0 Peter Maydell
2024-03-01 21:08 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 3/8] target/arm: use FIELD macro for CNTHCTL bit definitions Peter Maydell
2024-03-01 19:04 ` Philippe Mathieu-Daudé
2024-03-01 21:10 ` Richard Henderson
2024-03-01 21:19 ` Richard Henderson
2024-03-04 13:21 ` Peter Maydell
2024-03-04 17:02 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Peter Maydell
2024-03-01 21:11 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 5/8] target/arm: Implement new FEAT_ECV trap bits Peter Maydell
2024-03-01 21:37 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 6/8] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 Peter Maydell
2024-03-01 21:41 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling Peter Maydell
2024-03-01 21:54 ` Richard Henderson
2024-03-02 10:59 ` Peter Maydell
2024-03-01 18:32 ` Peter Maydell [this message]
2024-03-01 19:05 ` [PATCH 8/8] target/arm: Enable FEAT_ECV for 'max' CPU Philippe Mathieu-Daudé
2024-03-01 21:58 ` Richard Henderson
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