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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 18/41] target/sparc: Implement FNMUL
Date: Fri,  1 Mar 2024 19:15:38 -1000	[thread overview]
Message-ID: <20240302051601.53649-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240302051601.53649-1-richard.henderson@linaro.org>

Unlike FNADD, we cannot (ab)use muladd for this operation because

    -0.0 * +0.0 == -0.0
    -0.0 + +0.0 == +0.0

the addition step will lose the -0.0 product result before negation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/helper.h     |  3 +++
 target/sparc/fop_helper.c | 36 ++++++++++++++++++++++++++++++++++++
 target/sparc/translate.c  | 21 +++++++++++++++++++++
 target/sparc/insns.decode |  3 +++
 4 files changed, 63 insertions(+)

diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 37b22afd7f..926b579e97 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -54,6 +54,7 @@ DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64)
 DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
 DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64)
 DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32)
+DEF_HELPER_FLAGS_3(fnmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
 
 DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128)
 DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128)
@@ -65,8 +66,10 @@ DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32)
 DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
 DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32)
 DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32)
+DEF_HELPER_FLAGS_3(fnmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
 
 DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32)
+DEF_HELPER_FLAGS_3(fnsmuld, TCG_CALL_NO_WG, f64, env, f32, f32)
 DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64)
 
 DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_WG, f64, env, s32)
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
index 1de44d79c1..ea9d4ec235 100644
--- a/target/sparc/fop_helper.c
+++ b/target/sparc/fop_helper.c
@@ -359,6 +359,42 @@ float64 helper_fmaddd(CPUSPARCState *env, float64 s1,
     return ret;
 }
 
+float32 helper_fnmuls(CPUSPARCState *env, float32 src1, float32 src2)
+{
+    float32 ret = float32_mul(src1, src2, &env->fp_status);
+
+    /* NaN inputs or result do not get a sign change. */
+    if (!(get_float_exception_flags(&env->fp_status) & float_flag_invalid)) {
+        ret = float32_chs(ret);
+    }
+    check_ieee_exceptions(env, GETPC());
+    return ret;
+}
+
+float64 helper_fnmuld(CPUSPARCState *env, float64 src1, float64 src2)
+{
+    float64 ret = float64_mul(src1, src2, &env->fp_status);
+
+    if (!(get_float_exception_flags(&env->fp_status) & float_flag_invalid)) {
+        ret = float64_chs(ret);
+    }
+    check_ieee_exceptions(env, GETPC());
+    return ret;
+}
+
+float64 helper_fnsmuld(CPUSPARCState *env, float32 src1, float32 src2)
+{
+    float64 ret = float64_mul(float32_to_float64(src1, &env->fp_status),
+                              float32_to_float64(src2, &env->fp_status),
+                              &env->fp_status);
+
+    if (!(get_float_exception_flags(&env->fp_status) & float_flag_invalid)) {
+        ret = float64_chs(ret);
+    }
+    check_ieee_exceptions(env, GETPC());
+    return ret;
+}
+
 static uint32_t finish_fcmp(CPUSPARCState *env, FloatRelation r, uintptr_t ra)
 {
     check_ieee_exceptions(env, ra);
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 877847b884..b3714ada6a 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4776,6 +4776,7 @@ TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds)
 TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs)
 TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls)
 TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs)
+TRANS(FNMULs, VIS3, do_env_fff, a, gen_helper_fnmuls)
 
 static bool do_dff(DisasContext *dc, arg_r_r_r *a,
                    void (*func)(TCGv_i64, TCGv_i32, TCGv_i32))
@@ -4923,6 +4924,7 @@ TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd)
 TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd)
 TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld)
 TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd)
+TRANS(FNMULd, VIS3, do_env_ddd, a, gen_helper_fnmuld)
 
 static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a)
 {
@@ -4944,6 +4946,25 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a)
     return advance_pc(dc);
 }
 
+static bool trans_FNsMULd(DisasContext *dc, arg_r_r_r *a)
+{
+    TCGv_i64 dst;
+    TCGv_i32 src1, src2;
+
+    if (!avail_VIS3(dc)) {
+        return false;
+    }
+    if (gen_trap_ifnofpu(dc)) {
+        return true;
+    }
+    dst = tcg_temp_new_i64();
+    src1 = gen_load_fpr_F(dc, a->rs1);
+    src2 = gen_load_fpr_F(dc, a->rs2);
+    gen_helper_fnsmuld(dst, tcg_env, src1, src2);
+    gen_store_fpr_D(dc, a->rd, dst);
+    return advance_pc(dc);
+}
+
 static bool do_ffff(DisasContext *dc, arg_r_r_r_r *a,
                     void (*func)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
 {
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index dc524f5b8f..8c0df3004d 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -309,6 +309,8 @@ FDIVd       10 ..... 110100 ..... 0 0100 1110 .....        @d_d_d
 FDIVq       10 ..... 110100 ..... 0 0100 1111 .....        @q_q_q
 FNADDs      10 ..... 110100 ..... 0 0101 0001 .....        @r_r_r
 FNADDd      10 ..... 110100 ..... 0 0101 0010 .....        @d_d_d
+FNMULs      10 ..... 110100 ..... 0 0101 1001 .....        @r_r_r
+FNMULd      10 ..... 110100 ..... 0 0101 1010 .....        @d_d_d
 FHADDs      10 ..... 110100 ..... 0 0110 0001 .....        @r_r_r
 FHADDd      10 ..... 110100 ..... 0 0110 0010 .....        @d_d_d
 FHSUBs      10 ..... 110100 ..... 0 0110 0101 .....        @r_r_r
@@ -317,6 +319,7 @@ FsMULd      10 ..... 110100 ..... 0 0110 1001 .....        @d_r_r
 FdMULq      10 ..... 110100 ..... 0 0110 1110 .....        @q_d_d
 FNHADDs     10 ..... 110100 ..... 0 0111 0001 .....        @r_r_r
 FNHADDd     10 ..... 110100 ..... 0 0111 0010 .....        @d_d_d
+FNsMULd     10 ..... 110100 ..... 0 0111 1001 .....        @d_r_r
 FsTOx       10 ..... 110100 00000 0 1000 0001 .....        @r_r2
 FdTOx       10 ..... 110100 00000 0 1000 0010 .....        @r_d2
 FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @r_q2
-- 
2.34.1



  parent reply	other threads:[~2024-03-02  5:19 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-02  5:15 [PATCH 00/41] target/sparc: Implement VIS4 Richard Henderson
2024-03-02  5:15 ` [PATCH 01/41] linux-user/sparc: Add more hwcap bits for sparc64 Richard Henderson
2024-03-02  5:15 ` [PATCH 02/41] target/sparc: Fix FEXPAND Richard Henderson
2024-03-02  5:15 ` [PATCH 03/41] target/sparc: Fix FMUL8x16 Richard Henderson
2024-03-02  5:15 ` [PATCH 04/41] target/sparc: Fix FMUL8x16A{U,L} Richard Henderson
2024-04-30  8:07   ` Mark Cave-Ayland
2024-03-02  5:15 ` [PATCH 05/41] target/sparc: Fix FMULD8*X16 Richard Henderson
2024-03-02  5:15 ` [PATCH 06/41] target/sparc: Fix FPMERGE Richard Henderson
2024-03-02  5:15 ` [PATCH 07/41] target/sparc: Split out do_ms16b Richard Henderson
2024-03-02  5:15 ` [PATCH 08/41] target/sparc: Perform DFPREG/QFPREG in decodetree Richard Henderson
2024-05-10 15:18   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 09/41] target/sparc: Remove gen_dest_fpr_D Richard Henderson
2024-05-10 15:18   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 10/41] target/sparc: Remove cpu_fpr[] Richard Henderson
2024-03-02  5:15 ` [PATCH 11/41] target/sparc: Use gvec for VIS1 parallel add/sub Richard Henderson
2024-05-10 15:21   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 12/41] target/sparc: Implement FMAf extension Richard Henderson
2024-03-02  5:15 ` [PATCH 13/41] target/sparc: Add feature bits for VIS 3 Richard Henderson
2024-05-10 17:05   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 14/41] target/sparc: Implement ADDXC, ADDXCcc Richard Henderson
2024-05-10 16:16   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 15/41] target/sparc: Implement CMASK instructions Richard Henderson
2024-03-02  5:15 ` [PATCH 16/41] target/sparc: Implement FCHKSM16 Richard Henderson
2024-03-02  5:15 ` [PATCH 17/41] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD Richard Henderson
2024-03-02  5:15 ` Richard Henderson [this message]
2024-03-02  5:15 ` [PATCH 19/41] target/sparc: Implement FLCMP Richard Henderson
2024-03-02  5:15 ` [PATCH 20/41] target/sparc: Implement FMEAN16 Richard Henderson
2024-03-02  5:15 ` [PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64 Richard Henderson
2024-05-10 16:19   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 22/41] target/sparc: Implement FPADDS, FPSUBS Richard Henderson
2024-03-02  5:15 ` [PATCH 23/41] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 Richard Henderson
2024-03-02  5:15 ` [PATCH 24/41] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS Richard Henderson
2024-03-02  5:15 ` [PATCH 25/41] target/sparc: Implement LDXEFSR Richard Henderson
2024-03-02  5:15 ` [PATCH 26/41] target/sparc: Implement LZCNT Richard Henderson
2024-05-10 17:22   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 27/41] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd Richard Henderson
2024-03-02  5:15 ` [PATCH 28/41] target/sparc: Implement PDISTN Richard Henderson
2024-05-10 17:28   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 29/41] target/sparc: Implement UMULXHI Richard Henderson
2024-03-02  5:15 ` [PATCH 30/41] target/sparc: Implement XMULX Richard Henderson
2024-03-02  5:15 ` [PATCH 31/41] target/sparc: Enable VIS3 feature bit Richard Henderson
2024-03-02  5:15 ` [PATCH 32/41] target/sparc: Implement IMA extension Richard Henderson
2024-05-10 17:09   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 33/41] target/sparc: Add feature bit for VIS4 Richard Henderson
2024-05-10 17:05   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 34/41] target/sparc: Implement FALIGNDATAi Richard Henderson
2024-03-02  5:15 ` [PATCH 35/41] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS Richard Henderson
2024-05-10 16:20   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 36/41] target/sparc: Implement VIS4 comparisons Richard Henderson
2024-03-02  5:15 ` [PATCH 37/41] target/sparc: Implement FPMIN, FPMAX Richard Henderson
2024-05-10 17:11   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 38/41] target/sparc: Implement SUBXC, SUBXCcc Richard Henderson
2024-05-10 16:21   ` Philippe Mathieu-Daudé
2024-03-02  5:15 ` [PATCH 39/41] target/sparc: Implement MWAIT Richard Henderson
2024-03-02  5:16 ` [PATCH 40/41] target/sparc: Implement monitor asis Richard Henderson
2024-05-10 17:04   ` Philippe Mathieu-Daudé
2024-03-02  5:16 ` [PATCH 41/41] target/sparc: Enable VIS4 feature bit Richard Henderson
2024-05-10 17:16   ` Philippe Mathieu-Daudé
2024-05-10 17:31     ` Philippe Mathieu-Daudé
2024-03-05 10:20 ` [PATCH 00/41] target/sparc: Implement VIS4 Mark Cave-Ayland
2024-04-29 20:52 ` Mark Cave-Ayland
2024-04-29 21:02   ` Richard Henderson
2024-04-29 21:10     ` Mark Cave-Ayland

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