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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 06/41] target/sparc: Fix FPMERGE
Date: Fri,  1 Mar 2024 19:15:26 -1000	[thread overview]
Message-ID: <20240302051601.53649-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240302051601.53649-1-richard.henderson@linaro.org>

This instruction has f32 inputs, which changes the decode
of the register numbers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/helper.h     |  2 +-
 target/sparc/translate.c  |  2 +-
 target/sparc/vis_helper.c | 27 ++++++++++++++-------------
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 39ea8f9baf..f0576fb748 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -91,7 +91,7 @@ DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_WG, s64, env, f32)
 DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64)
 DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128)
 
-DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i32, i32)
 DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64)
 DEF_HELPER_FLAGS_2(fmul8x16a, TCG_CALL_NO_RWG_SE, i64, i32, s32)
 DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index edb97bc64e..6a6c259b06 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4612,6 +4612,7 @@ TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au)
 TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al)
 TRANS(FMULD8SUx16, VIS1, do_dff, a, gen_op_fmuld8sux16)
 TRANS(FMULD8ULx16, VIS1, do_dff, a, gen_op_fmuld8ulx16)
+TRANS(FPMERGE, VIS1, do_dff, a, gen_helper_fpmerge)
 
 static bool do_dfd(DisasContext *dc, arg_r_r_r *a,
                    void (*func)(TCGv_i64, TCGv_i32, TCGv_i64))
@@ -4652,7 +4653,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
 
 TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16)
 TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16)
-TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge)
 
 TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64)
 TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64)
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index eb1c4e47e9..89eea05ddb 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -74,22 +74,23 @@ typedef union {
     float32 f;
 } VIS32;
 
-uint64_t helper_fpmerge(uint64_t src1, uint64_t src2)
+uint64_t helper_fpmerge(uint32_t src1, uint32_t src2)
 {
-    VIS64 s, d;
+    VIS32 s1, s2;
+    VIS64 d;
 
-    s.ll = src1;
-    d.ll = src2;
+    s1.l = src1;
+    s2.l = src2;
+    d.ll = 0;
 
-    /* Reverse calculation order to handle overlap */
-    d.VIS_B64(7) = s.VIS_B64(3);
-    d.VIS_B64(6) = d.VIS_B64(3);
-    d.VIS_B64(5) = s.VIS_B64(2);
-    d.VIS_B64(4) = d.VIS_B64(2);
-    d.VIS_B64(3) = s.VIS_B64(1);
-    d.VIS_B64(2) = d.VIS_B64(1);
-    d.VIS_B64(1) = s.VIS_B64(0);
-    /* d.VIS_B64(0) = d.VIS_B64(0); */
+    d.VIS_B64(7) = s1.VIS_B32(3);
+    d.VIS_B64(6) = s2.VIS_B32(3);
+    d.VIS_B64(5) = s1.VIS_B32(2);
+    d.VIS_B64(4) = s2.VIS_B32(2);
+    d.VIS_B64(3) = s1.VIS_B32(1);
+    d.VIS_B64(2) = s2.VIS_B32(1);
+    d.VIS_B64(1) = s1.VIS_B32(0);
+    d.VIS_B64(0) = s2.VIS_B32(0);
 
     return d.ll;
 }
-- 
2.34.1



  parent reply	other threads:[~2024-03-02  5:18 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-02  5:15 [PATCH 00/41] target/sparc: Implement VIS4 Richard Henderson
2024-03-02  5:15 ` [PATCH 01/41] linux-user/sparc: Add more hwcap bits for sparc64 Richard Henderson
2024-03-02  5:15 ` [PATCH 02/41] target/sparc: Fix FEXPAND Richard Henderson
2024-03-02  5:15 ` [PATCH 03/41] target/sparc: Fix FMUL8x16 Richard Henderson
2024-03-02  5:15 ` [PATCH 04/41] target/sparc: Fix FMUL8x16A{U,L} Richard Henderson
2024-04-30  8:07   ` Mark Cave-Ayland
2024-03-02  5:15 ` [PATCH 05/41] target/sparc: Fix FMULD8*X16 Richard Henderson
2024-03-02  5:15 ` Richard Henderson [this message]
2024-03-02  5:15 ` [PATCH 07/41] target/sparc: Split out do_ms16b Richard Henderson
2024-03-02  5:15 ` [PATCH 08/41] target/sparc: Perform DFPREG/QFPREG in decodetree Richard Henderson
2024-03-02  5:15 ` [PATCH 09/41] target/sparc: Remove gen_dest_fpr_D Richard Henderson
2024-03-02  5:15 ` [PATCH 10/41] target/sparc: Remove cpu_fpr[] Richard Henderson
2024-03-02  5:15 ` [PATCH 11/41] target/sparc: Use gvec for VIS1 parallel add/sub Richard Henderson
2024-03-02  5:15 ` [PATCH 12/41] target/sparc: Implement FMAf extension Richard Henderson
2024-03-02  5:15 ` [PATCH 13/41] target/sparc: Add feature bits for VIS 3 Richard Henderson
2024-03-02  5:15 ` [PATCH 14/41] target/sparc: Implement ADDXC, ADDXCcc Richard Henderson
2024-03-02  5:15 ` [PATCH 15/41] target/sparc: Implement CMASK instructions Richard Henderson
2024-03-02  5:15 ` [PATCH 16/41] target/sparc: Implement FCHKSM16 Richard Henderson
2024-03-02  5:15 ` [PATCH 17/41] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD Richard Henderson
2024-03-02  5:15 ` [PATCH 18/41] target/sparc: Implement FNMUL Richard Henderson
2024-03-02  5:15 ` [PATCH 19/41] target/sparc: Implement FLCMP Richard Henderson
2024-03-02  5:15 ` [PATCH 20/41] target/sparc: Implement FMEAN16 Richard Henderson
2024-03-02  5:15 ` [PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64 Richard Henderson
2024-03-02  5:15 ` [PATCH 22/41] target/sparc: Implement FPADDS, FPSUBS Richard Henderson
2024-03-02  5:15 ` [PATCH 23/41] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 Richard Henderson
2024-03-02  5:15 ` [PATCH 24/41] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS Richard Henderson
2024-03-02  5:15 ` [PATCH 25/41] target/sparc: Implement LDXEFSR Richard Henderson
2024-03-02  5:15 ` [PATCH 26/41] target/sparc: Implement LZCNT Richard Henderson
2024-03-02  5:15 ` [PATCH 27/41] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd Richard Henderson
2024-03-02  5:15 ` [PATCH 28/41] target/sparc: Implement PDISTN Richard Henderson
2024-03-02  5:15 ` [PATCH 29/41] target/sparc: Implement UMULXHI Richard Henderson
2024-03-02  5:15 ` [PATCH 30/41] target/sparc: Implement XMULX Richard Henderson
2024-03-02  5:15 ` [PATCH 31/41] target/sparc: Enable VIS3 feature bit Richard Henderson
2024-03-02  5:15 ` [PATCH 32/41] target/sparc: Implement IMA extension Richard Henderson
2024-03-02  5:15 ` [PATCH 33/41] target/sparc: Add feature bit for VIS4 Richard Henderson
2024-03-02  5:15 ` [PATCH 34/41] target/sparc: Implement FALIGNDATAi Richard Henderson
2024-03-02  5:15 ` [PATCH 35/41] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS Richard Henderson
2024-03-02  5:15 ` [PATCH 36/41] target/sparc: Implement VIS4 comparisons Richard Henderson
2024-03-02  5:15 ` [PATCH 37/41] target/sparc: Implement FPMIN, FPMAX Richard Henderson
2024-03-02  5:15 ` [PATCH 38/41] target/sparc: Implement SUBXC, SUBXCcc Richard Henderson
2024-03-02  5:15 ` [PATCH 39/41] target/sparc: Implement MWAIT Richard Henderson
2024-03-02  5:16 ` [PATCH 40/41] target/sparc: Implement monitor asis Richard Henderson
2024-03-02  5:16 ` [PATCH 41/41] target/sparc: Enable VIS4 feature bit Richard Henderson
2024-03-05 10:20 ` [PATCH 00/41] target/sparc: Implement VIS4 Mark Cave-Ayland
2024-04-29 20:52 ` Mark Cave-Ayland
2024-04-29 21:02   ` Richard Henderson
2024-04-29 21:10     ` Mark Cave-Ayland

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