From: Claudiu <claudiu.beznea@tuxon.dev>
To: geert+renesas@glider.be, mturquette@baylibre.com,
sboyd@kernel.org, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
magnus.damm@gmail.com
Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
claudiu.beznea@tuxon.dev,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH v2 01/10] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
Date: Thu, 7 Mar 2024 16:07:19 +0200 [thread overview]
Message-ID: <20240307140728.190184-2-claudiu.beznea.uj@bp.renesas.com> (raw)
In-Reply-To: <20240307140728.190184-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v2:
- added "RZ/G2UL Only" comments to some defines
- added RZ/Five specific defines
include/dt-bindings/clock/r9a07g043-cpg.h | 52 +++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index 77cde8effdc7..ba9ea276c4a0 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -200,5 +200,57 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
+/* Power domain IDs. */
+#define R9A07G043_PD_ALWAYS_ON 0
+#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
+#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
+#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
+#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
+#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
+#define R9A07G043_PD_DMAC 6
+#define R9A07G043_PD_GTM0 7
+#define R9A07G043_PD_GTM1 8
+#define R9A07G043_PD_GTM2 9
+#define R9A07G043_PD_MTU 10
+#define R9A07G043_PD_POE3 11
+#define R9A07G043_PD_WDT0 12
+#define R9A07G043_PD_SPI 13
+#define R9A07G043_PD_SDHI0 14
+#define R9A07G043_PD_SDHI1 15
+#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
+#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
+#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
+#define R9A07G043_PD_SSI0 19
+#define R9A07G043_PD_SSI1 20
+#define R9A07G043_PD_SSI2 21
+#define R9A07G043_PD_SSI3 22
+#define R9A07G043_PD_SRC 23
+#define R9A07G043_PD_USB0 24
+#define R9A07G043_PD_USB1 25
+#define R9A07G043_PD_USB_PHY 26
+#define R9A07G043_PD_ETHER0 27
+#define R9A07G043_PD_ETHER1 28
+#define R9A07G043_PD_I2C0 29
+#define R9A07G043_PD_I2C1 30
+#define R9A07G043_PD_I2C2 31
+#define R9A07G043_PD_I2C3 32
+#define R9A07G043_PD_SCIF0 33
+#define R9A07G043_PD_SCIF1 34
+#define R9A07G043_PD_SCIF2 35
+#define R9A07G043_PD_SCIF3 36
+#define R9A07G043_PD_SCIF4 37
+#define R9A07G043_PD_SCI0 38
+#define R9A07G043_PD_SCI1 39
+#define R9A07G043_PD_IRDA 40
+#define R9A07G043_PD_RSPI0 41
+#define R9A07G043_PD_RSPI1 42
+#define R9A07G043_PD_RSPI2 43
+#define R9A07G043_PD_CANFD 44
+#define R9A07G043_PD_ADC 45
+#define R9A07G043_PD_TSU 46
+#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
+#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
+#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
+#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
--
2.39.2
next prev parent reply other threads:[~2024-03-07 14:07 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-07 14:07 [PATCH v2 00/10] clk: renesas: rzg2l: Add support for power domains Claudiu
2024-03-07 14:07 ` Claudiu [this message]
2024-03-11 15:04 ` [PATCH v2 01/10] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs Rob Herring
2024-03-14 15:58 ` Geert Uytterhoeven
2024-03-07 14:07 ` [PATCH v2 02/10] dt-bindings: clock: r9a07g044-cpg: " Claudiu
2024-03-11 15:04 ` Rob Herring
2024-03-07 14:07 ` [PATCH v2 03/10] dt-bindings: clock: r9a07g054-cpg: " Claudiu
2024-03-11 15:04 ` Rob Herring
2024-03-07 14:07 ` [PATCH v2 04/10] dt-bindings: clock: r9a08g045-cpg: " Claudiu
2024-03-11 15:04 ` Rob Herring
2024-03-07 14:07 ` [PATCH v2 05/10] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S Claudiu
2024-03-07 22:19 ` Rob Herring
2024-03-14 15:59 ` Geert Uytterhoeven
2024-03-07 14:07 ` [PATCH v2 06/10] clk: renesas: rzg2l: Extend power domain support Claudiu
2024-03-14 15:59 ` Geert Uytterhoeven
2024-03-07 14:07 ` [PATCH v2 07/10] clk: renesas: r9a08g045: Add support for power domains Claudiu
2024-03-14 16:01 ` Geert Uytterhoeven
2024-04-10 10:32 ` claudiu beznea
2024-03-07 14:07 ` [PATCH v2 08/10] clk: renesas: rzg2l-cpg: Add suspend/resume " Claudiu
2024-03-18 16:48 ` Geert Uytterhoeven
2024-04-10 10:31 ` claudiu beznea
2024-04-16 12:07 ` Ulf Hansson
2024-04-17 8:04 ` claudiu beznea
2024-04-17 9:39 ` Ulf Hansson
2024-04-17 11:31 ` claudiu beznea
2024-03-07 14:07 ` [PATCH v2 09/10] clk: renesas: r9a08g045: Add the RZG2L_PD_F_CONSOLE flag to scif0 PM domain Claudiu
2024-03-14 16:06 ` Geert Uytterhoeven
2024-03-15 5:45 ` claudiu beznea
2024-03-07 14:07 ` [PATCH v2 10/10] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1> Claudiu
2024-03-14 16:01 ` Geert Uytterhoeven
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