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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Frank Chang" <frank.chang@sifive.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PULL 15/34] target/riscv: Add missing include guard in pmu.h
Date: Fri,  8 Mar 2024 21:11:33 +1000	[thread overview]
Message-ID: <20240308111152.2856137-16-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240308111152.2856137-1-alistair.francis@wdc.com>

From: Frank Chang <frank.chang@sifive.com>

Add missing include guard in pmu.h to avoid the problem of double
inclusion.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240220110907.10479-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmu.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 505fc850d3..7c0ad661e0 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -16,6 +16,9 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef RISCV_PMU_H
+#define RISCV_PMU_H
+
 #include "cpu.h"
 #include "qapi/error.h"
 
@@ -31,3 +34,5 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
 void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
                           uint32_t ctr_idx);
+
+#endif /* RISCV_PMU_H */
-- 
2.44.0



  parent reply	other threads:[~2024-03-08 11:16 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-08 11:11 [PULL 00/34] riscv-to-apply queue Alistair Francis
2024-03-08 11:11 ` [PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt() Alistair Francis
2024-03-08 11:11 ` [PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location Alistair Francis
2024-03-08 11:11 ` [PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table Alistair Francis
2024-03-08 11:11 ` [PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM Alistair Francis
2024-03-08 11:11 ` [PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe Alistair Francis
2024-03-08 11:11 ` [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux Alistair Francis
2024-03-08 11:11 ` [PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Alistair Francis
2024-03-08 11:11 ` [PULL 08/34] target/riscv: add riscv,isa to named features Alistair Francis
2024-03-08 11:11 ` [PULL 09/34] target/riscv: add remaining " Alistair Francis
2024-03-11 13:47   ` Clément Chigot
2024-03-11 14:39     ` Daniel Henrique Barboza
2024-03-12  9:26       ` Daniel Henrique Barboza
2024-03-08 11:11 ` [PULL 10/34] target/riscv: Reset henvcfg to zero Alistair Francis
2024-03-08 11:11 ` [PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating Alistair Francis
2024-03-08 11:11 ` [PULL 12/34] target/riscv: Promote svade to a normal extension Alistair Francis
2024-03-08 11:11 ` [PULL 13/34] target/riscv: FIX xATP_MODE validation Alistair Francis
2024-03-08 11:11 ` [PULL 14/34] target/riscv: UPDATE xATP write CSR Alistair Francis
2024-03-08 11:11 ` Alistair Francis [this message]
2024-03-08 11:11 ` [PULL 16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables Alistair Francis
2024-03-08 11:11 ` [PULL 17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier Alistair Francis
2024-03-08 11:11 ` [PULL 18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support Alistair Francis
2024-03-08 11:11 ` [PULL 19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel Alistair Francis
2024-03-08 11:11 ` [PULL 20/34] tests/libqos: add riscv/virt machine nodes Alistair Francis
2024-03-25  9:20   ` Thomas Huth
2024-03-25 12:35     ` Daniel Henrique Barboza
2024-03-25 13:25       ` Christian Schoenebeck
2024-03-25 13:46         ` Thomas Huth
2024-03-25 13:44       ` Thomas Huth
2024-03-08 11:11 ` [PULL 21/34] RISC-V: Add support for Ztso Alistair Francis
2024-03-08 11:11 ` [PULL 22/34] linux-user/riscv: Add Ztso extension to hwprobe Alistair Francis
2024-03-08 11:11 ` [PULL 23/34] tests: riscv64: Use 'zfa' instead of 'Zfa' Alistair Francis
2024-03-08 11:11 ` [PULL 24/34] linux-headers: Update to Linux v6.8-rc6 Alistair Francis
2024-03-08 11:11 ` [PULL 25/34] target/riscv/kvm: update KVM exts to Linux 6.8 Alistair Francis
2024-03-08 11:11 ` [PULL 26/34] target/riscv: move ratified/frozen exts to non-experimental Alistair Francis
2024-03-08 11:11 ` [PULL 27/34] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit Alistair Francis
2024-03-08 11:11 ` [PULL 28/34] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Alistair Francis
2024-03-08 11:11 ` [PULL 29/34] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Alistair Francis
2024-03-08 11:11 ` [PULL 30/34] target/riscv: Fix shift count overflow Alistair Francis
2024-03-08 11:11 ` [PULL 31/34] hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode Alistair Francis
2024-03-08 11:11 ` [PULL 32/34] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation Alistair Francis
2024-03-08 11:11 ` [PULL 33/34] target/riscv: Fix privilege mode of G-stage translation for debugging Alistair Francis
2024-03-08 11:11 ` [PULL 34/34] target/riscv: fix ACPI MCFG table Alistair Francis
2024-03-08 16:48 ` [PULL 00/34] riscv-to-apply queue Peter Maydell

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