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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Palmer Dabbelt" <palmer@rivosinc.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Christoph Müllner" <christoph.muellner@vrull.eu>,
	"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PULL 21/34] RISC-V: Add support for Ztso
Date: Fri,  8 Mar 2024 21:11:39 +1000	[thread overview]
Message-ID: <20240308111152.2856137-22-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240308111152.2856137-1-alistair.francis@wdc.com>

From: Palmer Dabbelt <palmer@rivosinc.com>

The Ztso extension is already ratified, this adds it as a CPU property
and adds various fences throughout the port in order to allow TSO
targets to function on weaker hosts.  We need no fences for AMOs as
they're already SC, the places we need barriers are described.
These fences are placed in the RISC-V backend rather than TCG as is
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
likely soon dynamic) hart memory models.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/translate.c                |  3 +++
 target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
 target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
 6 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index be39870691..2040b90da0 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -71,6 +71,7 @@ struct RISCVCPUConfig {
     bool ext_zihintntl;
     bool ext_zihintpause;
     bool ext_zihpm;
+    bool ext_ztso;
     bool ext_smstateen;
     bool ext_sstc;
     bool ext_svadu;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 71bdedc9bb..37425e0e50 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -149,6 +149,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
     ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
     ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
+    ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
@@ -1500,6 +1501,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
     MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
     MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
+    MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
 
     MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
     MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 177418b2b9..ea5d52b2ef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -109,6 +109,8 @@ typedef struct DisasContext {
     /* PointerMasking extension */
     bool pm_mask_enabled;
     bool pm_base_enabled;
+    /* Ztso */
+    bool ztso;
     /* Use icount trigger for native debug */
     bool itrigger;
     /* FRM is known to contain a valid value. */
@@ -1196,6 +1198,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->cs = cs;
     ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
     ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
+    ctx->ztso = cpu->cfg.ext_ztso;
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 267930e5bc..4a9e4591d1 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -40,7 +40,11 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
     tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
-    if (a->aq) {
+    /*
+     * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
+     * AMOs.  Instead treat them like loads.
+     */
+    if (a->aq || ctx->ztso) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
 
@@ -76,9 +80,10 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     gen_set_label(l1);
     /*
      * Address comparison failure.  However, we still need to
-     * provide the memory barrier implied by AQ/RL.
+     * provide the memory barrier implied by AQ/RL/TSO.
      */
-    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+    TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
+    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
     gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
 
     gen_set_label(l2);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index faf6d65064..ad40d3e87f 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -266,12 +266,20 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
 
 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
+    bool out;
+
     decode_save_opc(ctx);
     if (get_xl(ctx) == MXL_RV128) {
-        return gen_load_i128(ctx, a, memop);
+        out = gen_load_i128(ctx, a, memop);
     } else {
-        return gen_load_tl(ctx, a, memop);
+        out = gen_load_tl(ctx, a, memop);
+    }
+
+    if (ctx->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
+
+    return out;
 }
 
 static bool trans_lb(DisasContext *ctx, arg_lb *a)
@@ -328,6 +336,10 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
     TCGv addr = get_address(ctx, a->rs1, a->imm);
     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 
+    if (ctx->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+    }
+
     tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9e101ab434..742008f58b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -636,8 +636,28 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
 
+    /*
+     * According to the specification
+     *
+     *   Additionally, if the Ztso extension is implemented, then vector memory
+     *   instructions in the V extension and Zve family of extensions follow
+     *   RVTSO at the instruction level.  The Ztso extension does not
+     *   strengthen the ordering of intra-instruction element accesses.
+     *
+     * as a result neither ordered nor unordered accesses from the V
+     * instructions need ordering within the loop but we do still need barriers
+     * around the loop.
+     */
+    if (is_store && s->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+    }
+
     fn(dest, mask, base, tcg_env, desc);
 
+    if (!is_store && s->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+    }
+
     if (!is_store) {
         mark_vs_dirty(s);
     }
-- 
2.44.0



  parent reply	other threads:[~2024-03-08 11:13 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-08 11:11 [PULL 00/34] riscv-to-apply queue Alistair Francis
2024-03-08 11:11 ` [PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt() Alistair Francis
2024-03-08 11:11 ` [PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location Alistair Francis
2024-03-08 11:11 ` [PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table Alistair Francis
2024-03-08 11:11 ` [PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM Alistair Francis
2024-03-08 11:11 ` [PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe Alistair Francis
2024-03-08 11:11 ` [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux Alistair Francis
2024-03-08 11:11 ` [PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Alistair Francis
2024-03-08 11:11 ` [PULL 08/34] target/riscv: add riscv,isa to named features Alistair Francis
2024-03-08 11:11 ` [PULL 09/34] target/riscv: add remaining " Alistair Francis
2024-03-11 13:47   ` Clément Chigot
2024-03-11 14:39     ` Daniel Henrique Barboza
2024-03-12  9:26       ` Daniel Henrique Barboza
2024-03-08 11:11 ` [PULL 10/34] target/riscv: Reset henvcfg to zero Alistair Francis
2024-03-08 11:11 ` [PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating Alistair Francis
2024-03-08 11:11 ` [PULL 12/34] target/riscv: Promote svade to a normal extension Alistair Francis
2024-03-08 11:11 ` [PULL 13/34] target/riscv: FIX xATP_MODE validation Alistair Francis
2024-03-08 11:11 ` [PULL 14/34] target/riscv: UPDATE xATP write CSR Alistair Francis
2024-03-08 11:11 ` [PULL 15/34] target/riscv: Add missing include guard in pmu.h Alistair Francis
2024-03-08 11:11 ` [PULL 16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables Alistair Francis
2024-03-08 11:11 ` [PULL 17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier Alistair Francis
2024-03-08 11:11 ` [PULL 18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support Alistair Francis
2024-03-08 11:11 ` [PULL 19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel Alistair Francis
2024-03-08 11:11 ` [PULL 20/34] tests/libqos: add riscv/virt machine nodes Alistair Francis
2024-03-25  9:20   ` Thomas Huth
2024-03-25 12:35     ` Daniel Henrique Barboza
2024-03-25 13:25       ` Christian Schoenebeck
2024-03-25 13:46         ` Thomas Huth
2024-03-25 13:44       ` Thomas Huth
2024-03-08 11:11 ` Alistair Francis [this message]
2024-03-08 11:11 ` [PULL 22/34] linux-user/riscv: Add Ztso extension to hwprobe Alistair Francis
2024-03-08 11:11 ` [PULL 23/34] tests: riscv64: Use 'zfa' instead of 'Zfa' Alistair Francis
2024-03-08 11:11 ` [PULL 24/34] linux-headers: Update to Linux v6.8-rc6 Alistair Francis
2024-03-08 11:11 ` [PULL 25/34] target/riscv/kvm: update KVM exts to Linux 6.8 Alistair Francis
2024-03-08 11:11 ` [PULL 26/34] target/riscv: move ratified/frozen exts to non-experimental Alistair Francis
2024-03-08 11:11 ` [PULL 27/34] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit Alistair Francis
2024-03-08 11:11 ` [PULL 28/34] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Alistair Francis
2024-03-08 11:11 ` [PULL 29/34] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Alistair Francis
2024-03-08 11:11 ` [PULL 30/34] target/riscv: Fix shift count overflow Alistair Francis
2024-03-08 11:11 ` [PULL 31/34] hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode Alistair Francis
2024-03-08 11:11 ` [PULL 32/34] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation Alistair Francis
2024-03-08 11:11 ` [PULL 33/34] target/riscv: Fix privilege mode of G-stage translation for debugging Alistair Francis
2024-03-08 11:11 ` [PULL 34/34] target/riscv: fix ACPI MCFG table Alistair Francis
2024-03-08 16:48 ` [PULL 00/34] riscv-to-apply queue Peter Maydell

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