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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <apatel@ventanamicro.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 32/34] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
Date: Fri,  8 Mar 2024 21:11:50 +1000	[thread overview]
Message-ID: <20240308111152.2856137-33-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240308111152.2856137-1-alistair.francis@wdc.com>

From: Anup Patel <apatel@ventanamicro.com>

The reads to in_clrip[x] registers return rectified input values of the
interrupt sources.

A rectified input value of an interrupt source is defined by the section
"4.5.2 Source configurations (sourcecfg[1]–sourcecfg[1023])" of the RISC-V
AIA specification as:
"rectified input value = (incoming wire value) XOR (source is inverted)"

Update the riscv_aplic_read_input_word() implementation to match the above.

Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240306095722.463296-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 775bb96164..6a7fbfa861 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -162,7 +162,7 @@ static bool is_kvm_aia(bool msimode)
 static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
                                             uint32_t word)
 {
-    uint32_t i, irq, ret = 0;
+    uint32_t i, irq, sourcecfg, sm, raw_input, irq_inverted, ret = 0;
 
     for (i = 0; i < 32; i++) {
         irq = word * 32 + i;
@@ -170,7 +170,20 @@ static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
             continue;
         }
 
-        ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
+        sourcecfg = aplic->sourcecfg[irq];
+        if (sourcecfg & APLIC_SOURCECFG_D) {
+            continue;
+        }
+
+        sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
+        if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+            continue;
+        }
+
+        raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0;
+        irq_inverted = (sm == APLIC_SOURCECFG_SM_LEVEL_LOW ||
+                        sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0;
+        ret |= (raw_input ^ irq_inverted) << i;
     }
 
     return ret;
-- 
2.44.0



  parent reply	other threads:[~2024-03-08 11:18 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-08 11:11 [PULL 00/34] riscv-to-apply queue Alistair Francis
2024-03-08 11:11 ` [PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt() Alistair Francis
2024-03-08 11:11 ` [PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location Alistair Francis
2024-03-08 11:11 ` [PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table Alistair Francis
2024-03-08 11:11 ` [PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM Alistair Francis
2024-03-08 11:11 ` [PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe Alistair Francis
2024-03-08 11:11 ` [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux Alistair Francis
2024-03-08 11:11 ` [PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Alistair Francis
2024-03-08 11:11 ` [PULL 08/34] target/riscv: add riscv,isa to named features Alistair Francis
2024-03-08 11:11 ` [PULL 09/34] target/riscv: add remaining " Alistair Francis
2024-03-11 13:47   ` Clément Chigot
2024-03-11 14:39     ` Daniel Henrique Barboza
2024-03-12  9:26       ` Daniel Henrique Barboza
2024-03-08 11:11 ` [PULL 10/34] target/riscv: Reset henvcfg to zero Alistair Francis
2024-03-08 11:11 ` [PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating Alistair Francis
2024-03-08 11:11 ` [PULL 12/34] target/riscv: Promote svade to a normal extension Alistair Francis
2024-03-08 11:11 ` [PULL 13/34] target/riscv: FIX xATP_MODE validation Alistair Francis
2024-03-08 11:11 ` [PULL 14/34] target/riscv: UPDATE xATP write CSR Alistair Francis
2024-03-08 11:11 ` [PULL 15/34] target/riscv: Add missing include guard in pmu.h Alistair Francis
2024-03-08 11:11 ` [PULL 16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables Alistair Francis
2024-03-08 11:11 ` [PULL 17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier Alistair Francis
2024-03-08 11:11 ` [PULL 18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support Alistair Francis
2024-03-08 11:11 ` [PULL 19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel Alistair Francis
2024-03-08 11:11 ` [PULL 20/34] tests/libqos: add riscv/virt machine nodes Alistair Francis
2024-03-25  9:20   ` Thomas Huth
2024-03-25 12:35     ` Daniel Henrique Barboza
2024-03-25 13:25       ` Christian Schoenebeck
2024-03-25 13:46         ` Thomas Huth
2024-03-25 13:44       ` Thomas Huth
2024-03-08 11:11 ` [PULL 21/34] RISC-V: Add support for Ztso Alistair Francis
2024-03-08 11:11 ` [PULL 22/34] linux-user/riscv: Add Ztso extension to hwprobe Alistair Francis
2024-03-08 11:11 ` [PULL 23/34] tests: riscv64: Use 'zfa' instead of 'Zfa' Alistair Francis
2024-03-08 11:11 ` [PULL 24/34] linux-headers: Update to Linux v6.8-rc6 Alistair Francis
2024-03-08 11:11 ` [PULL 25/34] target/riscv/kvm: update KVM exts to Linux 6.8 Alistair Francis
2024-03-08 11:11 ` [PULL 26/34] target/riscv: move ratified/frozen exts to non-experimental Alistair Francis
2024-03-08 11:11 ` [PULL 27/34] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit Alistair Francis
2024-03-08 11:11 ` [PULL 28/34] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Alistair Francis
2024-03-08 11:11 ` [PULL 29/34] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Alistair Francis
2024-03-08 11:11 ` [PULL 30/34] target/riscv: Fix shift count overflow Alistair Francis
2024-03-08 11:11 ` [PULL 31/34] hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode Alistair Francis
2024-03-08 11:11 ` Alistair Francis [this message]
2024-03-08 11:11 ` [PULL 33/34] target/riscv: Fix privilege mode of G-stage translation for debugging Alistair Francis
2024-03-08 11:11 ` [PULL 34/34] target/riscv: fix ACPI MCFG table Alistair Francis
2024-03-08 16:48 ` [PULL 00/34] riscv-to-apply queue Peter Maydell

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