From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-ppc@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>,
Harsh Prateek Bora <harshpb@linux.ibm.com>,
Chinmay Rath <rathc@linux.ibm.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 15/38] target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree
Date: Wed, 13 Mar 2024 02:58:26 +1000 [thread overview]
Message-ID: <20240312165851.2240242-16-npiggin@gmail.com> (raw)
In-Reply-To: <20240312165851.2240242-1-npiggin@gmail.com>
From: Chinmay Rath <rathc@linux.ibm.com>
This patch moves the below instructions to decodetree specification:
{add, subf}[c,e,me,ze][o][.] : XO-form
addic[.], subfic : D-form
addex : Z23-form
This patch introduces XO form instructions into decode tree
specification, for which all the four variations([o][.]) have been
handled with a single pattern. The changes were verified by validating
that the tcg ops generated by those instructions remain the same, which
were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/insn32.decode | 26 ++++
target/ppc/translate.c | 136 ---------------------
target/ppc/translate/fixedpoint-impl.c.inc | 70 +++++++++++
3 files changed, 96 insertions(+), 136 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 4fcf3af8d0..eada59f59f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -187,6 +187,12 @@
&X_a ra
@X_a ...... ra:3 .. ..... ..... .......... . &X_a
+&XO rt ra rb oe:bool rc:bool
+@XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO
+
+&XO_ta rt ra oe:bool rc:bool
+@XO_ta ...... rt:5 ra:5 ..... oe:1 ......... rc:1 &XO_ta
+
%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
@@ -322,10 +328,30 @@ CMPLI 001010 ... - . ..... ................ @D_bfu
### Fixed-Point Arithmetic Instructions
+ADD 011111 ..... ..... ..... . 100001010 . @XO
+ADDC 011111 ..... ..... ..... . 000001010 . @XO
+ADDE 011111 ..... ..... ..... . 010001010 . @XO
+
+# ADDEX is Z23-form, with CY=0; all other values for CY are reserved.
+# This works out the same as X-form.
+ADDEX 011111 ..... ..... ..... 00 10101010 - @X
+
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+ADDIC 001100 ..... ..... ................ @D
+ADDIC_ 001101 ..... ..... ................ @D
ADDPCIS 010011 ..... ..... .......... 00010 . @DX
+ADDME 011111 ..... ..... ----- . 011101010 . @XO_ta
+ADDZE 011111 ..... ..... ----- . 011001010 . @XO_ta
+
+SUBF 011111 ..... ..... ..... . 000101000 . @XO
+SUBFIC 001000 ..... ..... ................ @D
+SUBFC 011111 ..... ..... ..... . 000001000 . @XO
+SUBFE 011111 ..... ..... ..... . 010001000 . @XO
+
+SUBFME 011111 ..... ..... ----- . 011101000 . @XO_ta
+SUBFZE 011111 ..... ..... ----- . 011001000 . @XO_ta
## Fixed-Point Logical Instructions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 28fc7791af..4f6f7dcd89 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1735,61 +1735,6 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ret, t0);
}
}
-/* Add functions with two operands */
-#define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- ca, glue(ca, 32), \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* Add functions with one operand and one immediate */
-#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
- add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_constant_tl(const_val); \
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], t0, \
- ca, glue(ca, 32), \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-
-/* add add. addo addo. */
-GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
-GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
-/* addc addc. addco addco. */
-GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
-GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
-/* adde adde. addeo addeo. */
-GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
-/* addme addme. addmeo addmeo. */
-GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
-/* addex */
-GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
-/* addze addze. addzeo addzeo.*/
-GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addic addic.*/
-static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
-{
- TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
-}
-
-static void gen_addic(DisasContext *ctx)
-{
- gen_op_addic(ctx, 0);
-}
-
-static void gen_addic_(DisasContext *ctx)
-{
- gen_op_addic(ctx, 1);
-}
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -2210,47 +2155,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ret, t0);
}
}
-/* Sub functions with Two operands functions */
-#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* Sub functions with one operand and one immediate */
-#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_constant_tl(const_val); \
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], t0, \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* subf subf. subfo subfo. */
-GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
-GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
-/* subfc subfc. subfco subfco. */
-GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
-/* subfe subfe. subfeo subfo. */
-GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
-GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
-/* subfme subfme. subfmeo subfmeo. */
-GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
-/* subfze subfze. subfzeo subfzeo.*/
-GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
-
-/* subfic */
-static void gen_subfic(DisasContext *ctx)
-{
- TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- c, 0, 1, 0, 0);
-}
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
@@ -6524,8 +6428,6 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
@@ -6536,7 +6438,6 @@ GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
#endif
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
-GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
@@ -6747,25 +6648,6 @@ GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
#endif
-#undef GEN_INT_ARITH_ADD
-#undef GEN_INT_ARITH_ADD_CONST
-#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
-#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
-GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
-GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
-GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
-GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
-GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
-GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
-GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
-GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
-
#undef GEN_INT_ARITH_DIVW
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
@@ -6804,24 +6686,6 @@ GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
#endif
-#undef GEN_INT_ARITH_SUBF
-#undef GEN_INT_ARITH_SUBF_CONST
-#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
-#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
-GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
-GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
-GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
-GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
-GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
-GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
-GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
-
#undef GEN_LOGICAL1
#undef GEN_LOGICAL2
#define GEN_LOGICAL2(name, tcg_op, opc, type) \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 51c6fa7330..0c66465d96 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -325,6 +325,76 @@ static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
return true;
}
+static bool trans_ADDEX(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ cpu_ov, cpu_ov32, true, true, false, false);
+ return true;
+}
+
+static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
+ bool compute_ov, bool compute_rc0)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
+ tcg_constant_tl(a->si), cpu_ca, cpu_ca32,
+ add_ca, compute_ca, compute_ov, compute_rc0);
+ return true;
+}
+
+static bool do_add_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
+ bool compute_ca)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+static bool do_add_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
+ bool add_ca, bool compute_ca)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
+ cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+TRANS(ADD, do_add_XO, false, false);
+TRANS(ADDC, do_add_XO, false, true);
+TRANS(ADDE, do_add_XO, true, true);
+TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), true, true);
+TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true);
+TRANS(ADDIC, do_add_D, false, true, false, false);
+TRANS(ADDIC_, do_add_D, false, true, false, true);
+
+static bool trans_SUBFIC(DisasContext *ctx, arg_D *a)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
+ tcg_constant_tl(a->si), false, true, false, false);
+ return true;
+}
+
+static bool do_subf_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
+ bool compute_ca)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+static bool do_subf_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
+ bool add_ca, bool compute_ca)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
+ add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+TRANS(SUBF, do_subf_XO, false, false)
+TRANS(SUBFC, do_subf_XO, false, true)
+TRANS(SUBFE, do_subf_XO, true, true)
+TRANS(SUBFME, do_subf_const_XO, tcg_constant_tl(-1LL), true, true)
+TRANS(SUBFZE, do_subf_const_XO, tcg_constant_tl(0), true, true)
+
static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
{
gen_invalid(ctx);
--
2.42.0
next prev parent reply other threads:[~2024-03-12 17:00 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
2024-03-12 16:58 ` [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing Nicholas Piggin
2024-03-12 16:58 ` [PULL 02/38] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
2024-03-12 16:58 ` [PULL 03/38] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
2024-03-12 16:58 ` [PULL 04/38] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
2024-03-12 16:58 ` [PULL 05/38] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-03-12 16:58 ` [PULL 06/38] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
2024-03-12 16:58 ` [PULL 07/38] ppc/spapr: Remove copy-paste " Nicholas Piggin
2024-03-12 16:58 ` [PULL 08/38] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-03-12 16:58 ` [PULL 09/38] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-03-12 16:58 ` [PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant Nicholas Piggin
2024-03-12 16:58 ` [PULL 11/38] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-03-12 16:58 ` [PULL 12/38] MAINTAINERS: Remove myself as reviewer from PPC Nicholas Piggin
2024-03-12 16:58 ` [PULL 13/38] docs: Deprecate the pseries-2.12 machines Nicholas Piggin
2024-03-12 16:58 ` [PULL 14/38] docs/system/ppc: Document running Linux on AmigaNG machines Nicholas Piggin
2024-03-12 16:58 ` Nicholas Piggin [this message]
2024-03-12 16:58 ` [PULL 16/38] target/ppc: Add power10 pmu SPRs Nicholas Piggin
2024-03-12 16:58 ` [PULL 17/38] ppc/pnv: Improve pervasive topology calculation for big-core Nicholas Piggin
2024-03-12 16:58 ` [PULL 18/38] target/ppc: Use env_cpu for cpu_abort in excp_helper Nicholas Piggin
2024-03-12 16:58 ` [PULL 19/38] target/ppc: Readability improvements in exception handlers Nicholas Piggin
2024-03-12 16:58 ` [PULL 20/38] target/ppc: Add gen_exception_err_nip() function Nicholas Piggin
2024-03-12 16:58 ` [PULL 21/38] target/ppc: Clean up ifdefs in excp_helper.c, part 1 Nicholas Piggin
2024-03-12 16:58 ` [PULL 22/38] target/ppc: Clean up ifdefs in excp_helper.c, part 2 Nicholas Piggin
2024-03-12 16:58 ` [PULL 23/38] target/ppc: Clean up ifdefs in excp_helper.c, part 3 Nicholas Piggin
2024-03-12 16:58 ` [PULL 24/38] target/ppc: Remove interrupt handler wrapper functions Nicholas Piggin
2024-03-12 16:58 ` [PULL 25/38] spapr: nested: register nested-hv api hcalls only for cap-nested-hv Nicholas Piggin
2024-03-12 16:58 ` [PULL 26/38] spapr: nested: move nested part of spapr_get_pate into spapr_nested.c Nicholas Piggin
2024-03-12 16:58 ` [PULL 27/38] spapr: nested: Introduce SpaprMachineStateNested to store related info Nicholas Piggin
2024-03-12 16:58 ` [PULL 28/38] spapr: nested: keep nested-hv related code restricted to its API Nicholas Piggin
2024-03-12 16:58 ` [PULL 29/38] spapr: nested: Document Nested PAPR API Nicholas Piggin
2024-03-12 16:58 ` [PULL 30/38] spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls Nicholas Piggin
2024-03-12 16:58 ` [PULL 31/38] spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls Nicholas Piggin
2024-03-12 16:58 ` [PULL 32/38] spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall Nicholas Piggin
2024-03-12 16:58 ` [PULL 33/38] spapr: nested: Extend nested_ppc_state for nested PAPR API Nicholas Piggin
2024-03-12 16:58 ` [PULL 34/38] spapr: nested: Initialize the GSB elements lookup table Nicholas Piggin
2024-03-12 16:58 ` [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls Nicholas Piggin
2024-03-26 16:02 ` Peter Maydell
2024-03-27 5:41 ` Harsh Prateek Bora
2024-03-27 8:05 ` Thomas Huth
2024-03-28 15:25 ` Peter Maydell
2024-03-29 3:53 ` Harsh Prateek Bora
2024-03-12 16:58 ` [PULL 36/38] spapr: nested: Use correct source for parttbl info for nested PAPR API Nicholas Piggin
2024-03-12 16:58 ` [PULL 37/38] spapr: nested: Introduce H_GUEST_RUN_VCPU hcall Nicholas Piggin
2024-03-12 16:58 ` [PULL 38/38] spapr: nested: Introduce cap-nested-papr for Nested PAPR API Nicholas Piggin
2024-03-12 19:29 ` [PULL 00/38] ppc-for-9.0-2 queue Bernhard Beschow
2024-03-13 15:10 ` Peter Maydell
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