From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com
Cc: greentime.hu@sifive.com, conor.dooley@microchip.com,
guoren@linux.alibaba.com, bjorn@kernel.org,
"Andy Chiu" <andy.chiu@sifive.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Costa Shulyupin" <costa.shul@redhat.com>
Subject: [v2, 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface
Date: Thu, 14 Mar 2024 22:25:41 +0800 [thread overview]
Message-ID: <20240314142542.19957-7-andy.chiu@sifive.com> (raw)
In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com>
The following Vector subextensions for "embedded" platforms are added
into RISCV_HWPROBE_KEY_IMA_EXT_0:
- ZVE32X
- ZVE32F
- ZVE64X
- ZVE64F
- ZVE64D
Extensions end with X mean the platform don't have a Vector FPU.
Extensions end with F/D mean whether single (F) or double (D) precision
Vector operation is supported.
The number 32 or 64 follows from ZVE tells the maximum element length.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
Changelog v2:
- zve* extensions in hwprobe depends on whether kernel supports v, so
include them after has_vector(). Fix a typo. (Clément)
---
Documentation/arch/riscv/hwprobe.rst | 15 +++++++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++
arch/riscv/kernel/sys_hwprobe.c | 5 +++++
3 files changed, 25 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index b2bcc9eed9aa..d0b02e012e5d 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -188,6 +188,21 @@ The following keys are defined:
manual starting from commit 95cf1f9 ("Add changes requested by Ved
during signoff")
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
+ supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
+ supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
+ supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
+ supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
+ supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 9f2a8e3ff204..b9a0876e969f 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -59,6 +59,11 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 36)
+#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 37)
+#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 38)
+#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 39)
+#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 40)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index a7c56b41efd2..db7495001f27 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -113,6 +113,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZICOND);
if (has_vector()) {
+ EXT_KEY(ZVE32X);
+ EXT_KEY(ZVE32F);
+ EXT_KEY(ZVE64X);
+ EXT_KEY(ZVE64F);
+ EXT_KEY(ZVE64D);
EXT_KEY(ZVBB);
EXT_KEY(ZVBC);
EXT_KEY(ZVKB);
--
2.17.1
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next prev parent reply other threads:[~2024-03-14 14:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 14:25 [v2, 0/7] Support Zve32[xf] and Zve64[xfd] Vector subextensions Andy Chiu
2024-03-14 14:25 ` [v2, 1/7] riscv: vector: add a comment when calling riscv_setup_vsize() Andy Chiu
2024-03-14 14:25 ` [v2, 2/7] riscv: smp: fail booting up smp if inconsistent vlen is detected Andy Chiu
2024-03-14 14:25 ` [v2, 3/7] riscv: cpufeature: call match_isa_ext() for single-letter extensions Andy Chiu
2024-03-14 15:07 ` Clément Léger
2024-03-14 14:25 ` [v2, 4/7] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Andy Chiu
2024-03-14 15:11 ` Clément Léger
2024-03-14 14:25 ` [v2, 5/7] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description Andy Chiu
2024-03-14 22:04 ` Stefan O'Rear
2024-03-15 11:36 ` Krzysztof Kozlowski
2024-03-14 14:25 ` Andy Chiu [this message]
2024-03-14 15:28 ` [v2, 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Clément Léger
2024-03-14 14:25 ` [v2, 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X Andy Chiu
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