From: Jan Dakinevich <jan.dakinevich@salutedevices.com>
To: Jan Dakinevich <jan.dakinevich@salutedevices.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<alsa-devel@alsa-project.org>, <linux-sound@vger.kernel.org>,
<linux-gpio@vger.kernel.org>
Cc: <kernel@salutedevices.com>
Subject: [PATCH 03/25] dt-bindings: clock: meson: add A1 audio clock and reset controller bindings
Date: Fri, 15 Mar 2024 02:21:39 +0300 [thread overview]
Message-ID: <20240314232201.2102178-4-jan.dakinevich@salutedevices.com> (raw)
In-Reply-To: <20240314232201.2102178-1-jan.dakinevich@salutedevices.com>
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
.../bindings/clock/amlogic,a1-audio-clkc.yaml | 83 ++++++++++++
.../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++
.../reset/amlogic,meson-a1-audio-reset.h | 29 +++++
3 files changed, 234 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
new file mode 100644
index 000000000000..c76cad4da493
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A1 Audio Clock Control Unit and Reset Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jan Dakinevich <jan.dakinevich@salutedevices.com>
+
+properties:
+ compatible:
+ const: amlogic,a1-audio-clkc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: input main peripheral bus clock
+ - description: input dds_in
+ - description: input fixed pll div2
+ - description: input fixed pll div3
+ - description: input hifi_pll
+ - description: input oscillator (usually at 24MHz)
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: dds_in
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: hifi_pll
+ - const: xtal
+
+required:
+ - compatible
+ - '#clock-cells'
+ - '#reset-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+ #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+ audio {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_audio: audio-clock-controller@0 {
+ compatible = "amlogic,a1-audio-clkc";
+ reg = <0x0 0xfe050000 0x0 0xb0>,
+ <0x0 0xfe054800 0x0 0x20>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clkc_periphs CLKID_AUDIO>,
+ <&clkc_periphs CLKID_DDS_IN>,
+ <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "pclk",
+ "dds_in",
+ "fclk_div2",
+ "fclk_div3",
+ "hifi_pll",
+ "xtal";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
new file mode 100644
index 000000000000..3392974784e7
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef __A1_AUDIO_CLKC_BINDINGS_H
+#define __A1_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB 1
+#define AUD_CLKID_TDMIN_A 2
+#define AUD_CLKID_TDMIN_B 3
+#define AUD_CLKID_TDMIN_LB 4
+#define AUD_CLKID_LOOPBACK 5
+#define AUD_CLKID_TDMOUT_A 6
+#define AUD_CLKID_TDMOUT_B 7
+#define AUD_CLKID_FRDDR_A 8
+#define AUD_CLKID_FRDDR_B 9
+#define AUD_CLKID_TODDR_A 10
+#define AUD_CLKID_TODDR_B 11
+#define AUD_CLKID_SPDIFIN 12
+#define AUD_CLKID_RESAMPLE 13
+#define AUD_CLKID_EQDRC 14
+#define AUD_CLKID_LOCKER 15
+#define AUD_CLKID_MST_A_MCLK_SEL 16
+#define AUD_CLKID_MST_A_MCLK_DIV 17
+#define AUD_CLKID_MST_A_MCLK 18
+#define AUD_CLKID_MST_B_MCLK_SEL 19
+#define AUD_CLKID_MST_B_MCLK_DIV 20
+#define AUD_CLKID_MST_B_MCLK 21
+#define AUD_CLKID_MST_C_MCLK_SEL 22
+#define AUD_CLKID_MST_C_MCLK_DIV 23
+#define AUD_CLKID_MST_C_MCLK 24
+#define AUD_CLKID_MST_D_MCLK_SEL 25
+#define AUD_CLKID_MST_D_MCLK_DIV 26
+#define AUD_CLKID_MST_D_MCLK 27
+#define AUD_CLKID_SPDIFIN_CLK_SEL 28
+#define AUD_CLKID_SPDIFIN_CLK_DIV 29
+#define AUD_CLKID_SPDIFIN_CLK 30
+#define AUD_CLKID_RESAMPLE_CLK_SEL 31
+#define AUD_CLKID_RESAMPLE_CLK_DIV 32
+#define AUD_CLKID_RESAMPLE_CLK 33
+#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
+#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
+#define AUD_CLKID_LOCKER_IN_CLK 36
+#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
+#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
+#define AUD_CLKID_LOCKER_OUT_CLK 39
+#define AUD_CLKID_EQDRC_CLK_SEL 40
+#define AUD_CLKID_EQDRC_CLK_DIV 41
+#define AUD_CLKID_EQDRC_CLK 42
+#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
+#define AUD_CLKID_MST_A_SCLK_DIV 44
+#define AUD_CLKID_MST_A_SCLK_POST_EN 45
+#define AUD_CLKID_MST_A_SCLK 46
+#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
+#define AUD_CLKID_MST_B_SCLK_DIV 48
+#define AUD_CLKID_MST_B_SCLK_POST_EN 49
+#define AUD_CLKID_MST_B_SCLK 50
+#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
+#define AUD_CLKID_MST_C_SCLK_DIV 52
+#define AUD_CLKID_MST_C_SCLK_POST_EN 53
+#define AUD_CLKID_MST_C_SCLK 54
+#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
+#define AUD_CLKID_MST_D_SCLK_DIV 56
+#define AUD_CLKID_MST_D_SCLK_POST_EN 57
+#define AUD_CLKID_MST_D_SCLK 58
+#define AUD_CLKID_MST_A_LRCLK_DIV 59
+#define AUD_CLKID_MST_A_LRCLK 60
+#define AUD_CLKID_MST_B_LRCLK_DIV 61
+#define AUD_CLKID_MST_B_LRCLK 62
+#define AUD_CLKID_MST_C_LRCLK_DIV 63
+#define AUD_CLKID_MST_C_LRCLK 64
+#define AUD_CLKID_MST_D_LRCLK_DIV 65
+#define AUD_CLKID_MST_D_LRCLK 66
+#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
+#define AUD_CLKID_TDMIN_A_SCLK 70
+#define AUD_CLKID_TDMIN_A_LRCLK 71
+#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
+#define AUD_CLKID_TDMIN_B_SCLK 75
+#define AUD_CLKID_TDMIN_B_LRCLK 76
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
+#define AUD_CLKID_TDMIN_LB_SCLK 80
+#define AUD_CLKID_TDMIN_LB_LRCLK 81
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
+#define AUD_CLKID_TDMOUT_A_SCLK 85
+#define AUD_CLKID_TDMOUT_A_LRCLK 86
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
+#define AUD_CLKID_TDMOUT_B_SCLK 90
+#define AUD_CLKID_TDMOUT_B_LRCLK 91
+
+#define AUD2_CLKID_DDR_ARB 100
+#define AUD2_CLKID_PDM 101
+#define AUD2_CLKID_TDMIN_VAD 102
+#define AUD2_CLKID_TODDR_VAD 103
+#define AUD2_CLKID_VAD 104
+#define AUD2_CLKID_AUDIOTOP 105
+#define AUD2_CLKID_VAD_MCLK_SEL 106
+#define AUD2_CLKID_VAD_MCLK_DIV 107
+#define AUD2_CLKID_VAD_MCLK 108
+#define AUD2_CLKID_VAD_CLK_SEL 109
+#define AUD2_CLKID_VAD_CLK_DIV 110
+#define AUD2_CLKID_VAD_CLK 111
+#define AUD2_CLKID_PDM_DCLK_SEL 112
+#define AUD2_CLKID_PDM_DCLK_DIV 113
+#define AUD2_CLKID_PDM_DCLK 114
+#define AUD2_CLKID_PDM_SYSCLK_SEL 115
+#define AUD2_CLKID_PDM_SYSCLK_DIV 116
+#define AUD2_CLKID_PDM_SYSCLK 117
+
+#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
new file mode 100644
index 000000000000..6b7ad8ea3da2
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+
+#define AUD_RESET_DDRARB 0
+#define AUD_RESET_TDMIN_A 1
+#define AUD_RESET_TDMIN_B 2
+#define AUD_RESET_TDMIN_LB 3
+#define AUD_RESET_LOOPBACK 4
+#define AUD_RESET_TDMOUT_A 5
+#define AUD_RESET_TDMOUT_B 6
+#define AUD_RESET_FRDDR_A 7
+#define AUD_RESET_FRDDR_B 8
+#define AUD_RESET_TODDR_A 9
+#define AUD_RESET_TODDR_B 10
+#define AUD_RESET_SPDIFIN 11
+#define AUD_RESET_RESAMPLE 12
+#define AUD_RESET_EQDRC 13
+#define AUD_RESET_LOCKER 14
+#define AUD_RESET_TOACODEC 30
+#define AUD_RESET_CLKTREE 31
+
+#endif
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Jan Dakinevich <jan.dakinevich@salutedevices.com>
To: Jan Dakinevich <jan.dakinevich@salutedevices.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<alsa-devel@alsa-project.org>, <linux-sound@vger.kernel.org>,
<linux-gpio@vger.kernel.org>
Cc: <kernel@salutedevices.com>
Subject: [PATCH 03/25] dt-bindings: clock: meson: add A1 audio clock and reset controller bindings
Date: Fri, 15 Mar 2024 02:21:39 +0300 [thread overview]
Message-ID: <20240314232201.2102178-4-jan.dakinevich@salutedevices.com> (raw)
In-Reply-To: <20240314232201.2102178-1-jan.dakinevich@salutedevices.com>
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
.../bindings/clock/amlogic,a1-audio-clkc.yaml | 83 ++++++++++++
.../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++
.../reset/amlogic,meson-a1-audio-reset.h | 29 +++++
3 files changed, 234 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
new file mode 100644
index 000000000000..c76cad4da493
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A1 Audio Clock Control Unit and Reset Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jan Dakinevich <jan.dakinevich@salutedevices.com>
+
+properties:
+ compatible:
+ const: amlogic,a1-audio-clkc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: input main peripheral bus clock
+ - description: input dds_in
+ - description: input fixed pll div2
+ - description: input fixed pll div3
+ - description: input hifi_pll
+ - description: input oscillator (usually at 24MHz)
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: dds_in
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: hifi_pll
+ - const: xtal
+
+required:
+ - compatible
+ - '#clock-cells'
+ - '#reset-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+ #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+ audio {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_audio: audio-clock-controller@0 {
+ compatible = "amlogic,a1-audio-clkc";
+ reg = <0x0 0xfe050000 0x0 0xb0>,
+ <0x0 0xfe054800 0x0 0x20>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clkc_periphs CLKID_AUDIO>,
+ <&clkc_periphs CLKID_DDS_IN>,
+ <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "pclk",
+ "dds_in",
+ "fclk_div2",
+ "fclk_div3",
+ "hifi_pll",
+ "xtal";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
new file mode 100644
index 000000000000..3392974784e7
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef __A1_AUDIO_CLKC_BINDINGS_H
+#define __A1_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB 1
+#define AUD_CLKID_TDMIN_A 2
+#define AUD_CLKID_TDMIN_B 3
+#define AUD_CLKID_TDMIN_LB 4
+#define AUD_CLKID_LOOPBACK 5
+#define AUD_CLKID_TDMOUT_A 6
+#define AUD_CLKID_TDMOUT_B 7
+#define AUD_CLKID_FRDDR_A 8
+#define AUD_CLKID_FRDDR_B 9
+#define AUD_CLKID_TODDR_A 10
+#define AUD_CLKID_TODDR_B 11
+#define AUD_CLKID_SPDIFIN 12
+#define AUD_CLKID_RESAMPLE 13
+#define AUD_CLKID_EQDRC 14
+#define AUD_CLKID_LOCKER 15
+#define AUD_CLKID_MST_A_MCLK_SEL 16
+#define AUD_CLKID_MST_A_MCLK_DIV 17
+#define AUD_CLKID_MST_A_MCLK 18
+#define AUD_CLKID_MST_B_MCLK_SEL 19
+#define AUD_CLKID_MST_B_MCLK_DIV 20
+#define AUD_CLKID_MST_B_MCLK 21
+#define AUD_CLKID_MST_C_MCLK_SEL 22
+#define AUD_CLKID_MST_C_MCLK_DIV 23
+#define AUD_CLKID_MST_C_MCLK 24
+#define AUD_CLKID_MST_D_MCLK_SEL 25
+#define AUD_CLKID_MST_D_MCLK_DIV 26
+#define AUD_CLKID_MST_D_MCLK 27
+#define AUD_CLKID_SPDIFIN_CLK_SEL 28
+#define AUD_CLKID_SPDIFIN_CLK_DIV 29
+#define AUD_CLKID_SPDIFIN_CLK 30
+#define AUD_CLKID_RESAMPLE_CLK_SEL 31
+#define AUD_CLKID_RESAMPLE_CLK_DIV 32
+#define AUD_CLKID_RESAMPLE_CLK 33
+#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
+#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
+#define AUD_CLKID_LOCKER_IN_CLK 36
+#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
+#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
+#define AUD_CLKID_LOCKER_OUT_CLK 39
+#define AUD_CLKID_EQDRC_CLK_SEL 40
+#define AUD_CLKID_EQDRC_CLK_DIV 41
+#define AUD_CLKID_EQDRC_CLK 42
+#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
+#define AUD_CLKID_MST_A_SCLK_DIV 44
+#define AUD_CLKID_MST_A_SCLK_POST_EN 45
+#define AUD_CLKID_MST_A_SCLK 46
+#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
+#define AUD_CLKID_MST_B_SCLK_DIV 48
+#define AUD_CLKID_MST_B_SCLK_POST_EN 49
+#define AUD_CLKID_MST_B_SCLK 50
+#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
+#define AUD_CLKID_MST_C_SCLK_DIV 52
+#define AUD_CLKID_MST_C_SCLK_POST_EN 53
+#define AUD_CLKID_MST_C_SCLK 54
+#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
+#define AUD_CLKID_MST_D_SCLK_DIV 56
+#define AUD_CLKID_MST_D_SCLK_POST_EN 57
+#define AUD_CLKID_MST_D_SCLK 58
+#define AUD_CLKID_MST_A_LRCLK_DIV 59
+#define AUD_CLKID_MST_A_LRCLK 60
+#define AUD_CLKID_MST_B_LRCLK_DIV 61
+#define AUD_CLKID_MST_B_LRCLK 62
+#define AUD_CLKID_MST_C_LRCLK_DIV 63
+#define AUD_CLKID_MST_C_LRCLK 64
+#define AUD_CLKID_MST_D_LRCLK_DIV 65
+#define AUD_CLKID_MST_D_LRCLK 66
+#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
+#define AUD_CLKID_TDMIN_A_SCLK 70
+#define AUD_CLKID_TDMIN_A_LRCLK 71
+#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
+#define AUD_CLKID_TDMIN_B_SCLK 75
+#define AUD_CLKID_TDMIN_B_LRCLK 76
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
+#define AUD_CLKID_TDMIN_LB_SCLK 80
+#define AUD_CLKID_TDMIN_LB_LRCLK 81
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
+#define AUD_CLKID_TDMOUT_A_SCLK 85
+#define AUD_CLKID_TDMOUT_A_LRCLK 86
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
+#define AUD_CLKID_TDMOUT_B_SCLK 90
+#define AUD_CLKID_TDMOUT_B_LRCLK 91
+
+#define AUD2_CLKID_DDR_ARB 100
+#define AUD2_CLKID_PDM 101
+#define AUD2_CLKID_TDMIN_VAD 102
+#define AUD2_CLKID_TODDR_VAD 103
+#define AUD2_CLKID_VAD 104
+#define AUD2_CLKID_AUDIOTOP 105
+#define AUD2_CLKID_VAD_MCLK_SEL 106
+#define AUD2_CLKID_VAD_MCLK_DIV 107
+#define AUD2_CLKID_VAD_MCLK 108
+#define AUD2_CLKID_VAD_CLK_SEL 109
+#define AUD2_CLKID_VAD_CLK_DIV 110
+#define AUD2_CLKID_VAD_CLK 111
+#define AUD2_CLKID_PDM_DCLK_SEL 112
+#define AUD2_CLKID_PDM_DCLK_DIV 113
+#define AUD2_CLKID_PDM_DCLK 114
+#define AUD2_CLKID_PDM_SYSCLK_SEL 115
+#define AUD2_CLKID_PDM_SYSCLK_DIV 116
+#define AUD2_CLKID_PDM_SYSCLK 117
+
+#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
new file mode 100644
index 000000000000..6b7ad8ea3da2
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+
+#define AUD_RESET_DDRARB 0
+#define AUD_RESET_TDMIN_A 1
+#define AUD_RESET_TDMIN_B 2
+#define AUD_RESET_TDMIN_LB 3
+#define AUD_RESET_LOOPBACK 4
+#define AUD_RESET_TDMOUT_A 5
+#define AUD_RESET_TDMOUT_B 6
+#define AUD_RESET_FRDDR_A 7
+#define AUD_RESET_FRDDR_B 8
+#define AUD_RESET_TODDR_A 9
+#define AUD_RESET_TODDR_B 10
+#define AUD_RESET_SPDIFIN 11
+#define AUD_RESET_RESAMPLE 12
+#define AUD_RESET_EQDRC 13
+#define AUD_RESET_LOCKER 14
+#define AUD_RESET_TOACODEC 30
+#define AUD_RESET_CLKTREE 31
+
+#endif
--
2.34.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Jan Dakinevich <jan.dakinevich@salutedevices.com>
To: Jan Dakinevich <jan.dakinevich@salutedevices.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<alsa-devel@alsa-project.org>, <linux-sound@vger.kernel.org>,
<linux-gpio@vger.kernel.org>
Cc: <kernel@salutedevices.com>
Subject: [PATCH 03/25] dt-bindings: clock: meson: add A1 audio clock and reset controller bindings
Date: Fri, 15 Mar 2024 02:21:39 +0300 [thread overview]
Message-ID: <20240314232201.2102178-4-jan.dakinevich@salutedevices.com> (raw)
In-Reply-To: <20240314232201.2102178-1-jan.dakinevich@salutedevices.com>
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
.../bindings/clock/amlogic,a1-audio-clkc.yaml | 83 ++++++++++++
.../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++
.../reset/amlogic,meson-a1-audio-reset.h | 29 +++++
3 files changed, 234 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
new file mode 100644
index 000000000000..c76cad4da493
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A1 Audio Clock Control Unit and Reset Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jan Dakinevich <jan.dakinevich@salutedevices.com>
+
+properties:
+ compatible:
+ const: amlogic,a1-audio-clkc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: input main peripheral bus clock
+ - description: input dds_in
+ - description: input fixed pll div2
+ - description: input fixed pll div3
+ - description: input hifi_pll
+ - description: input oscillator (usually at 24MHz)
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: dds_in
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: hifi_pll
+ - const: xtal
+
+required:
+ - compatible
+ - '#clock-cells'
+ - '#reset-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+ #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+ audio {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_audio: audio-clock-controller@0 {
+ compatible = "amlogic,a1-audio-clkc";
+ reg = <0x0 0xfe050000 0x0 0xb0>,
+ <0x0 0xfe054800 0x0 0x20>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clkc_periphs CLKID_AUDIO>,
+ <&clkc_periphs CLKID_DDS_IN>,
+ <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "pclk",
+ "dds_in",
+ "fclk_div2",
+ "fclk_div3",
+ "hifi_pll",
+ "xtal";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
new file mode 100644
index 000000000000..3392974784e7
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef __A1_AUDIO_CLKC_BINDINGS_H
+#define __A1_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB 1
+#define AUD_CLKID_TDMIN_A 2
+#define AUD_CLKID_TDMIN_B 3
+#define AUD_CLKID_TDMIN_LB 4
+#define AUD_CLKID_LOOPBACK 5
+#define AUD_CLKID_TDMOUT_A 6
+#define AUD_CLKID_TDMOUT_B 7
+#define AUD_CLKID_FRDDR_A 8
+#define AUD_CLKID_FRDDR_B 9
+#define AUD_CLKID_TODDR_A 10
+#define AUD_CLKID_TODDR_B 11
+#define AUD_CLKID_SPDIFIN 12
+#define AUD_CLKID_RESAMPLE 13
+#define AUD_CLKID_EQDRC 14
+#define AUD_CLKID_LOCKER 15
+#define AUD_CLKID_MST_A_MCLK_SEL 16
+#define AUD_CLKID_MST_A_MCLK_DIV 17
+#define AUD_CLKID_MST_A_MCLK 18
+#define AUD_CLKID_MST_B_MCLK_SEL 19
+#define AUD_CLKID_MST_B_MCLK_DIV 20
+#define AUD_CLKID_MST_B_MCLK 21
+#define AUD_CLKID_MST_C_MCLK_SEL 22
+#define AUD_CLKID_MST_C_MCLK_DIV 23
+#define AUD_CLKID_MST_C_MCLK 24
+#define AUD_CLKID_MST_D_MCLK_SEL 25
+#define AUD_CLKID_MST_D_MCLK_DIV 26
+#define AUD_CLKID_MST_D_MCLK 27
+#define AUD_CLKID_SPDIFIN_CLK_SEL 28
+#define AUD_CLKID_SPDIFIN_CLK_DIV 29
+#define AUD_CLKID_SPDIFIN_CLK 30
+#define AUD_CLKID_RESAMPLE_CLK_SEL 31
+#define AUD_CLKID_RESAMPLE_CLK_DIV 32
+#define AUD_CLKID_RESAMPLE_CLK 33
+#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
+#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
+#define AUD_CLKID_LOCKER_IN_CLK 36
+#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
+#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
+#define AUD_CLKID_LOCKER_OUT_CLK 39
+#define AUD_CLKID_EQDRC_CLK_SEL 40
+#define AUD_CLKID_EQDRC_CLK_DIV 41
+#define AUD_CLKID_EQDRC_CLK 42
+#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
+#define AUD_CLKID_MST_A_SCLK_DIV 44
+#define AUD_CLKID_MST_A_SCLK_POST_EN 45
+#define AUD_CLKID_MST_A_SCLK 46
+#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
+#define AUD_CLKID_MST_B_SCLK_DIV 48
+#define AUD_CLKID_MST_B_SCLK_POST_EN 49
+#define AUD_CLKID_MST_B_SCLK 50
+#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
+#define AUD_CLKID_MST_C_SCLK_DIV 52
+#define AUD_CLKID_MST_C_SCLK_POST_EN 53
+#define AUD_CLKID_MST_C_SCLK 54
+#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
+#define AUD_CLKID_MST_D_SCLK_DIV 56
+#define AUD_CLKID_MST_D_SCLK_POST_EN 57
+#define AUD_CLKID_MST_D_SCLK 58
+#define AUD_CLKID_MST_A_LRCLK_DIV 59
+#define AUD_CLKID_MST_A_LRCLK 60
+#define AUD_CLKID_MST_B_LRCLK_DIV 61
+#define AUD_CLKID_MST_B_LRCLK 62
+#define AUD_CLKID_MST_C_LRCLK_DIV 63
+#define AUD_CLKID_MST_C_LRCLK 64
+#define AUD_CLKID_MST_D_LRCLK_DIV 65
+#define AUD_CLKID_MST_D_LRCLK 66
+#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
+#define AUD_CLKID_TDMIN_A_SCLK 70
+#define AUD_CLKID_TDMIN_A_LRCLK 71
+#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
+#define AUD_CLKID_TDMIN_B_SCLK 75
+#define AUD_CLKID_TDMIN_B_LRCLK 76
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
+#define AUD_CLKID_TDMIN_LB_SCLK 80
+#define AUD_CLKID_TDMIN_LB_LRCLK 81
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
+#define AUD_CLKID_TDMOUT_A_SCLK 85
+#define AUD_CLKID_TDMOUT_A_LRCLK 86
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
+#define AUD_CLKID_TDMOUT_B_SCLK 90
+#define AUD_CLKID_TDMOUT_B_LRCLK 91
+
+#define AUD2_CLKID_DDR_ARB 100
+#define AUD2_CLKID_PDM 101
+#define AUD2_CLKID_TDMIN_VAD 102
+#define AUD2_CLKID_TODDR_VAD 103
+#define AUD2_CLKID_VAD 104
+#define AUD2_CLKID_AUDIOTOP 105
+#define AUD2_CLKID_VAD_MCLK_SEL 106
+#define AUD2_CLKID_VAD_MCLK_DIV 107
+#define AUD2_CLKID_VAD_MCLK 108
+#define AUD2_CLKID_VAD_CLK_SEL 109
+#define AUD2_CLKID_VAD_CLK_DIV 110
+#define AUD2_CLKID_VAD_CLK 111
+#define AUD2_CLKID_PDM_DCLK_SEL 112
+#define AUD2_CLKID_PDM_DCLK_DIV 113
+#define AUD2_CLKID_PDM_DCLK 114
+#define AUD2_CLKID_PDM_SYSCLK_SEL 115
+#define AUD2_CLKID_PDM_SYSCLK_DIV 116
+#define AUD2_CLKID_PDM_SYSCLK 117
+
+#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
new file mode 100644
index 000000000000..6b7ad8ea3da2
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+
+#define AUD_RESET_DDRARB 0
+#define AUD_RESET_TDMIN_A 1
+#define AUD_RESET_TDMIN_B 2
+#define AUD_RESET_TDMIN_LB 3
+#define AUD_RESET_LOOPBACK 4
+#define AUD_RESET_TDMOUT_A 5
+#define AUD_RESET_TDMOUT_B 6
+#define AUD_RESET_FRDDR_A 7
+#define AUD_RESET_FRDDR_B 8
+#define AUD_RESET_TODDR_A 9
+#define AUD_RESET_TODDR_B 10
+#define AUD_RESET_SPDIFIN 11
+#define AUD_RESET_RESAMPLE 12
+#define AUD_RESET_EQDRC 13
+#define AUD_RESET_LOCKER 14
+#define AUD_RESET_TOACODEC 30
+#define AUD_RESET_CLKTREE 31
+
+#endif
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-03-14 23:23 UTC|newest]
Thread overview: 255+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 23:21 [PATCH 00/25] Introduce support of audio for Amlogic A1 SoC family Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 01/25] clk: meson: a1: restrict an amount of 'hifi_pll' params Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 8:58 ` Jerome Brunet
2024-03-15 8:58 ` Jerome Brunet
2024-03-15 8:58 ` Jerome Brunet
2024-03-17 14:17 ` Jan Dakinevich
2024-03-17 14:17 ` Jan Dakinevich
2024-03-17 14:17 ` Jan Dakinevich
2024-03-18 10:17 ` Jerome Brunet
2024-03-18 10:17 ` Jerome Brunet
2024-03-18 10:17 ` Jerome Brunet
2024-03-18 22:35 ` Jan Dakinevich
2024-03-18 22:35 ` Jan Dakinevich
2024-03-18 22:35 ` Jan Dakinevich
2024-03-19 8:21 ` Jerome Brunet
2024-03-19 8:21 ` Jerome Brunet
2024-03-19 8:21 ` Jerome Brunet
2024-03-19 13:53 ` Dmitry Rokosov
2024-03-19 13:53 ` Dmitry Rokosov
2024-03-19 13:53 ` Dmitry Rokosov
2024-03-14 23:21 ` [PATCH 02/25] clk: meson: axg: move reset controller's code to separate module Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich [this message]
2024-03-14 23:21 ` [PATCH 03/25] dt-bindings: clock: meson: add A1 audio clock and reset controller bindings Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 9:56 ` Krzysztof Kozlowski
2024-03-15 9:56 ` Krzysztof Kozlowski
2024-03-15 9:56 ` Krzysztof Kozlowski
2024-03-14 23:21 ` [PATCH 04/25] clk: meson: a1: add the audio clock controller driver Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 9:20 ` Jerome Brunet
2024-03-15 9:20 ` Jerome Brunet
2024-03-15 9:20 ` Jerome Brunet
2024-03-19 1:47 ` Jan Dakinevich
2024-03-19 1:47 ` Jan Dakinevich
2024-03-19 1:47 ` Jan Dakinevich
2024-03-19 8:30 ` Jerome Brunet
2024-03-19 8:30 ` Jerome Brunet
2024-03-19 8:30 ` Jerome Brunet
2024-03-23 18:02 ` Jan Dakinevich
2024-03-23 18:02 ` Jan Dakinevich
2024-03-23 18:02 ` Jan Dakinevich
2024-03-26 15:26 ` Jerome Brunet
2024-03-26 15:26 ` Jerome Brunet
2024-03-26 15:26 ` Jerome Brunet
2024-03-26 18:44 ` Jan Dakinevich
2024-03-26 18:44 ` Jan Dakinevich
2024-03-26 18:44 ` Jan Dakinevich
2024-03-27 12:57 ` Jerome Brunet
2024-03-27 12:57 ` Jerome Brunet
2024-03-27 12:57 ` Jerome Brunet
2024-03-14 23:21 ` [PATCH 05/25] ASoC: meson: codec-glue: add support for capture stream Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 06/25] ASoC: meson: g12a-toacodec: fix "Lane Select" width Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 10:00 ` Jerome Brunet
2024-03-15 10:00 ` Jerome Brunet
2024-03-15 10:00 ` Jerome Brunet
2024-03-15 13:17 ` Dan Carpenter
2024-03-15 13:17 ` Dan Carpenter
2024-03-15 13:17 ` Dan Carpenter
2024-03-24 17:51 ` Jan Dakinevich
2024-03-24 17:51 ` Jan Dakinevich
2024-03-24 17:51 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 07/25] ASoC: meson: g12a-toacodec: rework the definition of bits Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 08/25] ASoC: dt-bindings: meson: g12a-toacodec: add support for A1 SoC family Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 9:58 ` Krzysztof Kozlowski
2024-03-15 9:58 ` Krzysztof Kozlowski
2024-03-15 9:58 ` Krzysztof Kozlowski
2024-03-17 14:29 ` Jan Dakinevich
2024-03-17 14:29 ` Jan Dakinevich
2024-03-17 14:29 ` Jan Dakinevich
2024-03-17 14:46 ` Krzysztof Kozlowski
2024-03-17 14:46 ` Krzysztof Kozlowski
2024-03-17 14:46 ` Krzysztof Kozlowski
2024-03-17 15:11 ` Jan Dakinevich
2024-03-17 15:11 ` Jan Dakinevich
2024-03-17 15:11 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 09/25] ASoC: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 13:33 ` Mark Brown
2024-03-15 13:33 ` Mark Brown
2024-03-15 13:33 ` Mark Brown
2024-03-17 15:19 ` Jan Dakinevich
2024-03-17 15:19 ` Jan Dakinevich
2024-03-17 15:19 ` Jan Dakinevich
2024-03-18 10:42 ` Jerome Brunet
2024-03-18 10:42 ` Jerome Brunet
2024-03-18 10:42 ` Jerome Brunet
2024-03-18 13:30 ` Mark Brown
2024-03-18 13:30 ` Mark Brown
2024-03-18 13:30 ` Mark Brown
2024-03-14 23:21 ` [PATCH 10/25] ASoC: meson: t9015: prepare to adding new platforms Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 11/25] ASoC: dt-bindings: meson: t9015: add support for A1 SoC family Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-17 19:03 ` Rob Herring
2024-03-17 19:03 ` Rob Herring
2024-03-17 19:03 ` Rob Herring
2024-03-17 23:39 ` Jan Dakinevich
2024-03-17 23:39 ` Jan Dakinevich
2024-03-17 23:39 ` Jan Dakinevich
2024-03-18 7:46 ` Krzysztof Kozlowski
2024-03-18 7:46 ` Krzysztof Kozlowski
2024-03-18 7:46 ` Krzysztof Kozlowski
2024-03-14 23:21 ` [PATCH 12/25] ASoC: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 13:36 ` Mark Brown
2024-03-15 13:36 ` Mark Brown
2024-03-15 13:36 ` Mark Brown
2024-03-17 16:27 ` Jan Dakinevich
2024-03-17 16:27 ` Jan Dakinevich
2024-03-17 16:27 ` Jan Dakinevich
2024-03-18 13:48 ` Mark Brown
2024-03-18 13:48 ` Mark Brown
2024-03-18 13:48 ` Mark Brown
2024-03-18 22:43 ` Jan Dakinevich
2024-03-18 22:43 ` Jan Dakinevich
2024-03-18 22:43 ` Jan Dakinevich
2024-03-18 10:46 ` Jerome Brunet
2024-03-18 10:46 ` Jerome Brunet
2024-03-18 10:46 ` Jerome Brunet
2024-03-19 0:17 ` Jan Dakinevich
2024-03-19 0:17 ` Jan Dakinevich
2024-03-19 0:17 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 13/25] ASoC: dt-bindings: meson: axg-pdm: document 'sysrate' property Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 10:00 ` Krzysztof Kozlowski
2024-03-15 10:00 ` Krzysztof Kozlowski
2024-03-15 10:00 ` Krzysztof Kozlowski
2024-03-15 10:22 ` Jerome Brunet
2024-03-15 10:22 ` Jerome Brunet
2024-03-15 10:22 ` Jerome Brunet
2024-03-17 15:52 ` Jan Dakinevich
2024-03-17 15:52 ` Jan Dakinevich
2024-03-17 15:52 ` Jan Dakinevich
2024-03-18 10:55 ` Jerome Brunet
2024-03-18 10:55 ` Jerome Brunet
2024-03-18 10:55 ` Jerome Brunet
2024-03-18 12:19 ` Jerome Brunet
2024-03-18 12:19 ` Jerome Brunet
2024-03-18 12:19 ` Jerome Brunet
2024-03-19 0:30 ` Jan Dakinevich
2024-03-19 0:30 ` Jan Dakinevich
2024-03-19 0:30 ` Jan Dakinevich
2024-03-19 0:35 ` Jan Dakinevich
2024-03-19 0:35 ` Jan Dakinevich
2024-03-19 0:35 ` Jan Dakinevich
2024-03-19 5:17 ` Krzysztof Kozlowski
2024-03-19 5:17 ` Krzysztof Kozlowski
2024-03-19 5:17 ` Krzysztof Kozlowski
2024-03-17 15:55 ` Jan Dakinevich
2024-03-17 15:55 ` Jan Dakinevich
2024-03-17 15:55 ` Jan Dakinevich
2024-03-17 16:27 ` Krzysztof Kozlowski
2024-03-17 16:27 ` Krzysztof Kozlowski
2024-03-17 16:27 ` Krzysztof Kozlowski
2024-03-17 16:35 ` Jan Dakinevich
2024-03-17 16:35 ` Jan Dakinevich
2024-03-17 16:35 ` Jan Dakinevich
2024-03-19 5:17 ` Krzysztof Kozlowski
2024-03-19 5:17 ` Krzysztof Kozlowski
2024-03-19 5:17 ` Krzysztof Kozlowski
2024-03-14 23:21 ` [PATCH 14/25] ASoC: meson: axg-pdm: introduce " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 15/25] pinctrl/meson: fix typo in PDM's pin name Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 16/25] ASoC: dt-bindings: meson: meson-axg-audio-arb: claim support of A1 SoC family Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-17 19:10 ` Rob Herring
2024-03-17 19:10 ` Rob Herring
2024-03-17 19:10 ` Rob Herring
2024-03-14 23:21 ` [PATCH 17/25] ASoC: dt-bindings: meson: axg-fifo: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-17 19:13 ` Rob Herring
2024-03-17 19:13 ` Rob Herring
2024-03-17 19:13 ` Rob Herring
2024-03-14 23:21 ` [PATCH 18/25] ASoC: dt-bindings: meson: axg-pdm: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-17 19:14 ` Rob Herring
2024-03-17 19:14 ` Rob Herring
2024-03-17 19:14 ` Rob Herring
2024-03-14 23:21 ` [PATCH 19/25] ASoC: dt-bindings: meson: axg-sound-card: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 10:06 ` Jerome Brunet
2024-03-15 10:06 ` Jerome Brunet
2024-03-15 10:06 ` Jerome Brunet
2024-03-17 16:39 ` Jan Dakinevich
2024-03-17 16:39 ` Jan Dakinevich
2024-03-17 16:39 ` Jan Dakinevich
2024-03-14 23:21 ` [PATCH 20/25] ASoC: dt-bindings: meson: axg-tdm-formatters: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-17 19:16 ` Rob Herring
2024-03-17 19:16 ` Rob Herring
2024-03-17 19:16 ` Rob Herring
2024-03-14 23:21 ` [PATCH 21/25] ASoC: dt-bindings: meson: axg-tdm-iface: " Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-15 10:13 ` Jerome Brunet
2024-03-15 10:13 ` Jerome Brunet
2024-03-15 10:13 ` Jerome Brunet
2024-03-14 23:21 ` [PATCH 22/25] ASoC: dt-bindings: meson: introduce link-name optional property Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-17 19:45 ` Rob Herring
2024-03-17 19:45 ` Rob Herring
2024-03-17 19:45 ` Rob Herring
2024-03-18 7:27 ` Dmitry Rokosov
2024-03-18 7:27 ` Dmitry Rokosov
2024-03-18 7:27 ` Dmitry Rokosov
2024-03-14 23:21 ` [PATCH 23/25] ASoC: meson: implement link-name optional property in meson card utils Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:21 ` Jan Dakinevich
2024-03-14 23:22 ` [PATCH 24/25] arm64: dts: meson: a1: add audio devices Jan Dakinevich
2024-03-14 23:22 ` Jan Dakinevich
2024-03-14 23:22 ` Jan Dakinevich
2024-03-14 23:22 ` [PATCH 25/25] arm64: dts: ad402: enable audio Jan Dakinevich
2024-03-14 23:22 ` Jan Dakinevich
2024-03-14 23:22 ` Jan Dakinevich
2024-03-15 10:01 ` [PATCH 00/25] Introduce support of audio for Amlogic A1 SoC family Jerome Brunet
2024-03-15 10:01 ` Jerome Brunet
2024-03-15 10:01 ` Jerome Brunet
2024-03-15 15:50 ` Rob Herring
2024-03-15 15:50 ` Rob Herring
2024-03-15 15:50 ` Rob Herring
2024-03-15 16:53 ` Neil Armstrong
2024-03-15 16:53 ` Neil Armstrong
2024-03-15 16:53 ` Neil Armstrong
2024-03-18 7:30 ` Dmitry Rokosov
2024-03-18 7:30 ` Dmitry Rokosov
2024-03-18 7:30 ` Dmitry Rokosov
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