From: Neil Armstrong <neil.armstrong@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong <neil.armstrong@linaro.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH v2 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs Date: Fri, 22 Mar 2024 10:42:38 +0100 [thread overview] Message-ID: <20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org> (raw) In-Reply-To: <20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++++++++++++++++--- include/dt-bindings/phy/phy-qcom-qmp.h | 4 ++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index ba966a78a128..14ac341b1577 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -88,11 +88,11 @@ properties: - description: offset of PCIe 4-lane configuration register - description: offset of configuration bit for this PHY - "#clock-cells": - const: 0 + "#clock-cells": true clock-output-names: - maxItems: 1 + minItems: 1 + maxItems: 2 "#phy-cells": const: 0 @@ -213,6 +213,27 @@ allOf: reset-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy + - qcom,sm8650-qmp-gen4x2-pcie-phy + then: + properties: + clock-output-names: + minItems: 2 + "#clock-cells": + const: 1 + else: + properties: + clock-output-names: + maxItems: 1 + "#clock-cells": + const: 0 + examples: - | #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h index 4edec4c5b224..6b43ea9e0051 100644 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ b/include/dt-bindings/phy/phy-qcom-qmp.h @@ -17,4 +17,8 @@ #define QMP_USB43DP_USB3_PHY 0 #define QMP_USB43DP_DP_PHY 1 +/* QMP PCIE PHYs */ +#define QMP_PCIE_PIPE_CLK 0 +#define QMP_PCIE_PHY_AUX_CLK 1 + #endif /* _DT_BINDINGS_PHY_QMP */ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <neil.armstrong@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong <neil.armstrong@linaro.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH v2 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs Date: Fri, 22 Mar 2024 10:42:38 +0100 [thread overview] Message-ID: <20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org> (raw) In-Reply-To: <20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++++++++++++++++--- include/dt-bindings/phy/phy-qcom-qmp.h | 4 ++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index ba966a78a128..14ac341b1577 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -88,11 +88,11 @@ properties: - description: offset of PCIe 4-lane configuration register - description: offset of configuration bit for this PHY - "#clock-cells": - const: 0 + "#clock-cells": true clock-output-names: - maxItems: 1 + minItems: 1 + maxItems: 2 "#phy-cells": const: 0 @@ -213,6 +213,27 @@ allOf: reset-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy + - qcom,sm8650-qmp-gen4x2-pcie-phy + then: + properties: + clock-output-names: + minItems: 2 + "#clock-cells": + const: 1 + else: + properties: + clock-output-names: + maxItems: 1 + "#clock-cells": + const: 0 + examples: - | #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h index 4edec4c5b224..6b43ea9e0051 100644 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ b/include/dt-bindings/phy/phy-qcom-qmp.h @@ -17,4 +17,8 @@ #define QMP_USB43DP_USB3_PHY 0 #define QMP_USB43DP_DP_PHY 1 +/* QMP PCIE PHYs */ +#define QMP_PCIE_PIPE_CLK 0 +#define QMP_PCIE_PHY_AUX_CLK 1 + #endif /* _DT_BINDINGS_PHY_QMP */ -- 2.34.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2024-03-22 9:42 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-22 9:42 [PATCH v2 0/7] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong [this message] 2024-03-22 9:42 ` [PATCH v2 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs Neil Armstrong 2024-03-22 9:42 ` [PATCH v2 2/7] phy: qcom: qmp-pcie: refactor clock register code Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-03-22 10:38 ` Dmitry Baryshkov 2024-03-22 10:38 ` Dmitry Baryshkov 2024-03-22 9:42 ` [PATCH v2 3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-03-22 10:41 ` Dmitry Baryshkov 2024-03-22 10:41 ` Dmitry Baryshkov 2024-03-22 10:45 ` Neil Armstrong 2024-03-22 10:45 ` Neil Armstrong 2024-03-22 11:59 ` Dmitry Baryshkov 2024-03-22 11:59 ` Dmitry Baryshkov 2024-03-22 9:42 ` [PATCH v2 4/7] phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-03-22 10:41 ` Dmitry Baryshkov 2024-03-22 10:41 ` Dmitry Baryshkov 2024-03-22 9:42 ` [PATCH v2 5/7] arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-03-22 9:42 ` [PATCH v2 6/7] arm64: dts: qcom: sm8550: " Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-03-22 9:42 ` [PATCH v2 7/7] arm64: dts: qcom: sm8650: " Neil Armstrong 2024-03-22 9:42 ` Neil Armstrong 2024-04-05 17:09 ` (subset) [PATCH v2 0/7] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Vinod Koul 2024-04-05 17:09 ` Vinod Koul
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