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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
	Jim Shu <jim.shu@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 12/15] hw/intc: Update APLIC IDC after claiming iforce register
Date: Fri, 22 Mar 2024 18:53:16 +1000	[thread overview]
Message-ID: <20240322085319.1758843-13-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com>

From: Frank Chang <frank.chang@sifive.com>

Currently, QEMU only sets the iforce register to 0 and returns early
when claiming the iforce register. However, this may leave mip.meip
remains at 1 if a spurious external interrupt triggered by iforce
register is the only pending interrupt to be claimed, and the interrupt
cannot be lowered as expected.

This commit fixes this issue by calling riscv_aplic_idc_update() to
update the IDC status after the iforce register is claimed.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240321104951.12104-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 6a7fbfa861..fc5df0d598 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -488,6 +488,7 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
 
     if (!topi) {
         aplic->iforce[idc] = 0;
+        riscv_aplic_idc_update(aplic, idc);
         return 0;
     }
 
-- 
2.44.0



  parent reply	other threads:[~2024-03-22  8:54 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-22  8:53 [PULL 00/15] riscv-to-apply queue Alistair Francis
2024-03-22  8:53 ` [PULL 01/15] target/riscv: do not enable all named features by default Alistair Francis
2024-03-22  8:53 ` [PULL 02/15] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Alistair Francis
2024-03-22  8:53 ` [PULL 03/15] trans_rvv.c.inc: set vstart = 0 in int scalar move insns Alistair Francis
2024-03-22  8:53 ` [PULL 04/15] target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess Alistair Francis
2024-03-22  8:53 ` [PULL 05/15] target/riscv: always clear vstart in whole vec move insns Alistair Francis
2024-03-22  8:53 ` [PULL 06/15] target/riscv: always clear vstart for ldst_whole insns Alistair Francis
2024-03-22  8:53 ` [PULL 07/15] target/riscv/vector_helpers: do early exit when vstart >= vl Alistair Francis
2024-03-22  8:53 ` [PULL 08/15] target/riscv: remove 'over' brconds from vector trans Alistair Francis
2024-03-22  8:53 ` [PULL 09/15] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Alistair Francis
2024-03-22  8:53 ` [PULL 10/15] target/riscv: enable 'vstart_eq_zero' in the end of insns Alistair Francis
2024-03-22  8:53 ` [PULL 11/15] target/riscv/vector_helper.c: optimize loops in ldst helpers Alistair Francis
2024-03-22  8:53 ` Alistair Francis [this message]
2024-03-22  8:53 ` [PULL 13/15] target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin Alistair Francis
2024-03-22  8:53 ` [PULL 14/15] target/riscv: Fix mode in riscv_tlb_fill Alistair Francis
2024-03-22  8:53 ` [PULL 15/15] target/riscv/kvm: fix timebase-frequency when using KVM acceleration Alistair Francis
2024-03-22 12:58 ` [PULL 00/15] riscv-to-apply queue Peter Maydell
2024-03-22 17:16 ` Michael Tokarev
2024-03-22 19:46   ` Daniel Henrique Barboza
2024-03-24 15:07     ` Michael Tokarev
2024-03-24 18:12       ` Daniel Henrique Barboza
2024-03-26  9:53         ` Michael Tokarev
2024-03-26  9:56           ` Alistair Francis
2024-03-26 12:09             ` Daniel Henrique Barboza
2024-03-27 10:13             ` Michael Tokarev

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