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From: Jinjie Ruan via <qemu-devel@nongnu.org>
To: <peter.maydell@linaro.org>, <eduardo@habkost.net>,
	<marcel.apfelbaum@gmail.com>, <philmd@linaro.org>,
	<wangyanan55@huawei.com>, <richard.henderson@linaro.org>,
	<qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>
Cc: <ruanjinjie@huawei.com>
Subject: [PATCH v10 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI
Date: Mon, 25 Mar 2024 08:48:42 +0000	[thread overview]
Message-ID: <20240325084854.3010562-12-ruanjinjie@huawei.com> (raw)
In-Reply-To: <20240325084854.3010562-1-ruanjinjie@huawei.com>

Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v4:
- Add Reviewed-by.
v3:
- Add support for VNMI.
---
 hw/intc/arm_gicv3_common.c         | 6 ++++++
 include/hw/intc/arm_gic_common.h   | 2 ++
 include/hw/intc/arm_gicv3_common.h | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index cb55c72681..c52f060026 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -299,6 +299,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
     for (i = 0; i < s->num_cpu; i++) {
         sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
     }
+    for (i = 0; i < s->num_cpu; i++) {
+        sysbus_init_irq(sbd, &s->cpu[i].parent_nmi);
+    }
+    for (i = 0; i < s->num_cpu; i++) {
+        sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi);
+    }
 
     memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
                           "gicv3_dist", 0x10000);
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index 7080375008..97fea4102d 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -71,6 +71,8 @@ struct GICState {
     qemu_irq parent_fiq[GIC_NCPU];
     qemu_irq parent_virq[GIC_NCPU];
     qemu_irq parent_vfiq[GIC_NCPU];
+    qemu_irq parent_nmi[GIC_NCPU];
+    qemu_irq parent_vnmi[GIC_NCPU];
     qemu_irq maintenance_irq[GIC_NCPU];
 
     /* GICD_CTLR; for a GIC with the security extensions the NS banked version
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 4e2fb518e7..7324c7d983 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -155,6 +155,8 @@ struct GICv3CPUState {
     qemu_irq parent_fiq;
     qemu_irq parent_virq;
     qemu_irq parent_vfiq;
+    qemu_irq parent_nmi;
+    qemu_irq parent_vnmi;
 
     /* Redistributor */
     uint32_t level;                  /* Current IRQ level */
-- 
2.34.1



  parent reply	other threads:[~2024-03-25  8:54 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-25  8:48 [PATCH v10 00/23] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 02/23] target/arm: Add PSTATE.ALLINT Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 04/23] target/arm: Implement ALLINT MSR (immediate) Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 05/23] target/arm: Support MSR access to ALLINT Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 06/23] target/arm: Add support for Non-maskable Interrupt Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 07/23] target/arm: Add support for NMI in arm_phys_excp_target_el() Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 09/23] target/arm: Handle PSTATE.ALLINT on taking an exception Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU Jinjie Ruan via
2024-03-25  8:48 ` Jinjie Ruan via [this message]
2024-03-28 14:55   ` [PATCH v10 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI Peter Maydell
2024-03-25  8:48 ` [PATCH v10 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 13/23] hw/intc: Enable FEAT_GICv3_NMI Feature Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 14/23] hw/intc/arm_gicv3: Add irq non-maskable property Jinjie Ruan via
2024-03-28 14:54   ` Peter Maydell
2024-03-30  1:42     ` Jinjie Ruan via
2024-03-30 14:45       ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 15/23] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 Jinjie Ruan via
2024-03-28 14:56   ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 16/23] hw/intc/arm_gicv3: Implement GICD_INMIR Jinjie Ruan via
2024-03-28 14:57   ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Jinjie Ruan via
2024-03-28 14:50   ` Peter Maydell
2024-03-30  2:44     ` Jinjie Ruan via
2024-03-30 14:48       ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() Jinjie Ruan via
2024-03-28 19:27   ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 19/23] hw/intc/arm_gicv3: Implement NMI interrupt prioirty Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 20/23] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 21/23] hw/intc/arm_gicv3: Report the VINMI interrupt Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 22/23] target/arm: Add FEAT_NMI to max Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 23/23] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC Jinjie Ruan via

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