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From: Bard Liao <yung-chuan.liao@linux.intel.com>
To: linux-sound@vger.kernel.org, vkoul@kernel.org
Cc: vinod.koul@linaro.org, linux-kernel@vger.kernel.org,
	pierre-louis.bossart@linux.intel.com, bard.liao@intel.com
Subject: [PATCH 5/7] soundwire: intel_ace2x: move and extend clock selection
Date: Tue, 26 Mar 2024 09:20:28 +0000	[thread overview]
Message-ID: <20240326092030.1062802-6-yung-chuan.liao@linux.intel.com> (raw)
In-Reply-To: <20240326092030.1062802-1-yung-chuan.liao@linux.intel.com>

From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

The input clock to the SoundWire IP can be
38.4 MHz (xtal clock source)
24.576 MHz (audio cardinal clock)
96 MHz (internal Audio PLL)

This patch moves the clock selection outside the mutex and add the new
choices for 24.576 and 96 MHz, but doesn't add any functionality.
Follow-up patches will add support for clock selection.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
---
 drivers/soundwire/intel_ace2x.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2x.c
index 8280baa3254b..abdd651a185c 100644
--- a/drivers/soundwire/intel_ace2x.c
+++ b/drivers/soundwire/intel_ace2x.c
@@ -74,20 +74,29 @@ static int intel_link_power_up(struct sdw_intel *sdw)
 	struct sdw_master_prop *prop = &bus->prop;
 	u32 *shim_mask = sdw->link_res->shim_mask;
 	unsigned int link_id = sdw->instance;
+	u32 clock_source;
 	u32 syncprd;
 	int ret;
 
+	if (prop->mclk_freq % 6000000) {
+		if (prop->mclk_freq % 2400000) {
+			syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576;
+			clock_source = SDW_SHIM2_MLCS_CARDINAL_CLK;
+		} else {
+			syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
+			clock_source = SDW_SHIM2_MLCS_XTAL_CLK;
+		}
+	} else {
+		syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96;
+		clock_source = SDW_SHIM2_MLCS_AUDIO_PLL_CLK;
+	}
+
 	mutex_lock(sdw->link_res->shim_lock);
 
 	if (!*shim_mask) {
 		/* we first need to program the SyncPRD/CPU registers */
 		dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
 
-		if (prop->mclk_freq % 6000000)
-			syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
-		else
-			syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
-
 		ret =  hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd);
 		if (ret < 0) {
 			dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n",
-- 
2.34.1


  parent reply	other threads:[~2024-03-26  9:20 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-26  9:20 [PATCH 0/7] soundwire: add support for link clock source selection Bard Liao
2024-03-26  9:20 ` [PATCH 1/7] soundwire: cadence: show the bus frequency and frame shape Bard Liao
2024-03-26  9:20 ` [PATCH 2/7] soundwire: bus: extend base clock checks to 96 MHz Bard Liao
2024-03-26  9:20 ` [PATCH 3/7] soundwire: intel: add more values for SYNCPRD Bard Liao
2024-03-26  9:20 ` [PATCH 4/7] soundwire: intel: add support for MeteorLake additional clocks Bard Liao
2024-03-26  9:20 ` Bard Liao [this message]
2024-03-26  9:20 ` [PATCH 6/7] soundwire: intel_ace2.x: power-up first before setting SYNCPRD Bard Liao
2024-03-26  9:20 ` [PATCH 7/7] soundwire: intel_ace2x: set the clock source Bard Liao
2024-04-05 11:52 ` [PATCH 0/7] soundwire: add support for link clock source selection Vinod Koul

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