From: Conor Dooley <conor@kernel.org> To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>, "Daire McNamara" <daire.mcnamara@microchip.com>, "Jamie Gibbons" <jamie.gibbons@microchip.com>, "Valentina Fernandez" <valentina.fernandezalanis@microchip.com>, "Linus Walleij" <linus.walleij@linaro.org>, "Bartosz Golaszewski" <brgl@bgdev.pl>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support Date: Wed, 27 Mar 2024 12:24:37 +0000 [thread overview] Message-ID: <20240327-procurer-rascal-33bca7d5d14b@spud> (raw) In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> From: Jamie Gibbons <jamie.gibbons@microchip.com> The GPIO controllers on PolarFire SoC were based on the "soft" IP CoreGPIO, but the inp/outp registers are at different offsets. Add compatible to allow for support of both sets of offsets. The soft core will not always have interrupts wired up, so only enforce them for the "hard" core on PolarFire SoC. Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index d481e78958a7..6884dacb2865 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - microchip,mpfs-gpio + - microchip,coregpio-rtl-v3 reg: maxItems: 1 @@ -62,12 +63,21 @@ patternProperties: - gpio-hog - gpios +allOf: + - if: + properties: + compatible: + contains: + const: microchip,mpfs-gpio + then: + required: + - interrupts + - "#interrupt-cells" + - interrupt-controller + required: - compatible - reg - - interrupts - - "#interrupt-cells" - - interrupt-controller - "#gpio-cells" - gpio-controller - clocks -- 2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>, "Daire McNamara" <daire.mcnamara@microchip.com>, "Jamie Gibbons" <jamie.gibbons@microchip.com>, "Valentina Fernandez" <valentina.fernandezalanis@microchip.com>, "Linus Walleij" <linus.walleij@linaro.org>, "Bartosz Golaszewski" <brgl@bgdev.pl>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support Date: Wed, 27 Mar 2024 12:24:37 +0000 [thread overview] Message-ID: <20240327-procurer-rascal-33bca7d5d14b@spud> (raw) In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> From: Jamie Gibbons <jamie.gibbons@microchip.com> The GPIO controllers on PolarFire SoC were based on the "soft" IP CoreGPIO, but the inp/outp registers are at different offsets. Add compatible to allow for support of both sets of offsets. The soft core will not always have interrupts wired up, so only enforce them for the "hard" core on PolarFire SoC. Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index d481e78958a7..6884dacb2865 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - microchip,mpfs-gpio + - microchip,coregpio-rtl-v3 reg: maxItems: 1 @@ -62,12 +63,21 @@ patternProperties: - gpio-hog - gpios +allOf: + - if: + properties: + compatible: + contains: + const: microchip,mpfs-gpio + then: + required: + - interrupts + - "#interrupt-cells" + - interrupt-controller + required: - compatible - reg - - interrupts - - "#interrupt-cells" - - interrupt-controller - "#gpio-cells" - gpio-controller - clocks -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-27 12:25 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-27 12:24 [PATCH v1 0/5] BeagleV Fire support Conor Dooley 2024-03-27 12:24 ` Conor Dooley 2024-03-27 12:24 ` [PATCH v1 1/5] dt-bindings: riscv: microchip: document beaglev-fire Conor Dooley 2024-03-27 12:24 ` Conor Dooley 2024-03-27 17:56 ` Rob Herring 2024-03-27 17:56 ` Rob Herring 2024-03-27 12:24 ` Conor Dooley [this message] 2024-03-27 12:24 ` [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support Conor Dooley 2024-03-27 17:57 ` Rob Herring 2024-03-27 17:57 ` Rob Herring 2024-03-29 10:28 ` Bartosz Golaszewski 2024-03-29 10:28 ` Bartosz Golaszewski 2024-03-27 12:24 ` [PATCH v1 3/5] dt-bindings: gpio: mpfs: allow gpio-line-names Conor Dooley 2024-03-27 12:24 ` Conor Dooley 2024-03-27 17:57 ` Rob Herring 2024-03-27 17:57 ` Rob Herring 2024-03-29 10:29 ` Bartosz Golaszewski 2024-03-29 10:29 ` Bartosz Golaszewski 2024-03-27 12:24 ` [PATCH v1 4/5] dt-bindings: PCI: microchip: increase number of items in ranges property Conor Dooley 2024-03-27 12:24 ` Conor Dooley 2024-03-27 17:57 ` Rob Herring 2024-03-27 17:57 ` Rob Herring 2024-04-19 15:57 ` Conor Dooley 2024-04-19 15:57 ` Conor Dooley 2024-03-27 12:24 ` [PATCH v1 5/5] riscv: dts: microchip: add an initial devicetree for the BeagleV Fire Conor Dooley 2024-03-27 12:24 ` Conor Dooley
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