From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti <alexghiti@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Yunhui Cui <cuiyunhui@bytedance.com>, Samuel Holland <samuel.holland@sifive.com> Subject: [PATCH v6 13/13] riscv: mm: Always use an ASID to flush mm contexts Date: Tue, 26 Mar 2024 21:49:54 -0700 [thread overview] Message-ID: <20240327045035.368512-14-samuel.holland@sifive.com> (raw) In-Reply-To: <20240327045035.368512-1-samuel.holland@sifive.com> Even if multiple ASIDs are not supported, using the single-ASID variant of the sfence.vma instruction preserves TLB entries for global (kernel) pages. So it is always more efficient to use the single-ASID code path. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- (no changes since v5) Changes in v5: - Leave use_asid_allocator declared in asm/mmu_context.h Changes in v4: - There is now only one copy of __flush_tlb_range() Changes in v2: - Update both copies of __flush_tlb_range() arch/riscv/mm/tlbflush.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 35266dd9a9a2..44e7ed4e194f 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -109,8 +109,7 @@ static void __flush_tlb_range(struct cpumask *cmask, unsigned long asid, static inline unsigned long get_mm_asid(struct mm_struct *mm) { - return static_branch_unlikely(&use_asid_allocator) ? - cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID; + return cntx2asid(atomic_long_read(&mm->context.id)); } void flush_tlb_mm(struct mm_struct *mm) -- 2.43.1
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti <alexghiti@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Yunhui Cui <cuiyunhui@bytedance.com>, Samuel Holland <samuel.holland@sifive.com> Subject: [PATCH v6 13/13] riscv: mm: Always use an ASID to flush mm contexts Date: Tue, 26 Mar 2024 21:49:54 -0700 [thread overview] Message-ID: <20240327045035.368512-14-samuel.holland@sifive.com> (raw) In-Reply-To: <20240327045035.368512-1-samuel.holland@sifive.com> Even if multiple ASIDs are not supported, using the single-ASID variant of the sfence.vma instruction preserves TLB entries for global (kernel) pages. So it is always more efficient to use the single-ASID code path. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- (no changes since v5) Changes in v5: - Leave use_asid_allocator declared in asm/mmu_context.h Changes in v4: - There is now only one copy of __flush_tlb_range() Changes in v2: - Update both copies of __flush_tlb_range() arch/riscv/mm/tlbflush.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 35266dd9a9a2..44e7ed4e194f 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -109,8 +109,7 @@ static void __flush_tlb_range(struct cpumask *cmask, unsigned long asid, static inline unsigned long get_mm_asid(struct mm_struct *mm) { - return static_branch_unlikely(&use_asid_allocator) ? - cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID; + return cntx2asid(atomic_long_read(&mm->context.id)); } void flush_tlb_mm(struct mm_struct *mm) -- 2.43.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-27 4:51 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-27 4:49 [PATCH v6 00/13] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` [PATCH v6 01/13] riscv: Flush the instruction cache during SMP bringup Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-04-24 20:50 ` Alexandre Ghiti 2024-04-24 20:50 ` Alexandre Ghiti 2024-03-27 4:49 ` [PATCH v6 02/13] riscv: Factor out page table TLB synchronization Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-04-04 7:48 ` Alexandre Ghiti 2024-04-04 7:48 ` Alexandre Ghiti 2024-03-27 4:49 ` [PATCH v6 03/13] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-04-04 7:56 ` Alexandre Ghiti 2024-04-04 7:56 ` Alexandre Ghiti 2024-03-27 4:49 ` [PATCH v6 04/13] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` [PATCH v6 05/13] riscv: Only send remote fences when some other CPU is online Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 6:16 ` [External] " yunhui cui 2024-03-27 6:16 ` yunhui cui 2024-03-27 20:14 ` Samuel Holland 2024-03-27 20:14 ` Samuel Holland 2024-03-28 2:21 ` yunhui cui 2024-03-28 2:21 ` yunhui cui 2024-04-04 8:04 ` Alexandre Ghiti 2024-04-04 8:04 ` Alexandre Ghiti 2024-03-27 4:49 ` [PATCH v6 06/13] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 6:23 ` [External] " yunhui cui 2024-03-27 6:23 ` yunhui cui 2024-03-27 4:49 ` [PATCH v6 07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` [PATCH v6 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 6:27 ` [External] " yunhui cui 2024-03-27 6:27 ` yunhui cui 2024-03-27 4:49 ` [PATCH v6 09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` [PATCH v6 10/13] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` [PATCH v6 11/13] riscv: mm: Make asid_bits a local variable Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` [PATCH v6 12/13] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland 2024-03-27 4:49 ` Samuel Holland 2024-03-27 4:49 ` Samuel Holland [this message] 2024-03-27 4:49 ` [PATCH v6 13/13] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20240327045035.368512-14-samuel.holland@sifive.com \ --to=samuel.holland@sifive.com \ --cc=alexghiti@rivosinc.com \ --cc=cuiyunhui@bytedance.com \ --cc=jszhang@kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mm@kvack.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.