From: "Christoph Müllner" <christoph.muellner@vrull.eu> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, "Björn Töpel" <bjorn@kernel.org>, "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>, "Heiko Stuebner" <heiko@sntech.de>, "Cooper Qu" <cooper.qu@linux.alibaba.com>, "Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>, "Huang Tao" <eric.huang@linux.alibaba.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Andrew Jones" <ajones@ventanamicro.com>, "Conor Dooley" <conor@kernel.org> Cc: "Christoph Müllner" <christoph.muellner@vrull.eu> Subject: [PATCH 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata Date: Wed, 27 Mar 2024 11:31:30 +0100 [thread overview] Message-ID: <20240327103130.3651950-3-christoph.muellner@vrull.eu> (raw) In-Reply-To: <20240327103130.3651950-1-christoph.muellner@vrull.eu> T-Head's MAEE mechanism (non-compatible equivalent of RVI's Svpbmt) is currently assumed for all T-Head harts. However, QEMU recently decided to drop acceptance of guests that write reserved bits in PTEs. As MAEE uses reserved bits in PTEs and Linux applies the MAEE errata for all T-Head harts, this broke the Linux startup on QEMU emulations of the C906 emulation. This patch attempts to address this issue by testing the MAEE bit in TH_MXSTATUS CSR. As the TH_MXSTATUS CSR is only accessible in M-mode this patch depends on M-mode firmware that handles this for us transparently. As this patch breaks Linux bootup on all C9xx machines with MAEE, which don't have M-mode firmware that handles the access to the TH_MXSTATUS CSR, this patch is marked as RFC. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- arch/riscv/errata/thead/errata.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 8c8a8a4b0421..dd7bf6c62a35 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,6 +19,9 @@ #include <asm/patch.h> #include <asm/vendorid_list.h> +#define CSR_TH_MXSTATUS 0x7c0 +#define MXSTATUS_MAEE _AC(0x200000, UL) + static bool errata_probe_maee(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -28,11 +31,14 @@ static bool errata_probe_maee(unsigned int stage, if (arch_id != 0 || impid != 0) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || - stage == RISCV_ALTERNATIVES_MODULE) - return true; + if (stage != RISCV_ALTERNATIVES_EARLY_BOOT && + stage != RISCV_ALTERNATIVES_MODULE) + return false; - return false; + if (!(csr_read(CSR_TH_MXSTATUS) & MXSTATUS_MAEE)) + return false; + + return true; } /* -- 2.44.0
WARNING: multiple messages have this Message-ID (diff)
From: "Christoph Müllner" <christoph.muellner@vrull.eu> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, "Björn Töpel" <bjorn@kernel.org>, "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>, "Heiko Stuebner" <heiko@sntech.de>, "Cooper Qu" <cooper.qu@linux.alibaba.com>, "Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>, "Huang Tao" <eric.huang@linux.alibaba.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Andrew Jones" <ajones@ventanamicro.com>, "Conor Dooley" <conor@kernel.org> Cc: "Christoph Müllner" <christoph.muellner@vrull.eu> Subject: [PATCH 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata Date: Wed, 27 Mar 2024 11:31:30 +0100 [thread overview] Message-ID: <20240327103130.3651950-3-christoph.muellner@vrull.eu> (raw) In-Reply-To: <20240327103130.3651950-1-christoph.muellner@vrull.eu> T-Head's MAEE mechanism (non-compatible equivalent of RVI's Svpbmt) is currently assumed for all T-Head harts. However, QEMU recently decided to drop acceptance of guests that write reserved bits in PTEs. As MAEE uses reserved bits in PTEs and Linux applies the MAEE errata for all T-Head harts, this broke the Linux startup on QEMU emulations of the C906 emulation. This patch attempts to address this issue by testing the MAEE bit in TH_MXSTATUS CSR. As the TH_MXSTATUS CSR is only accessible in M-mode this patch depends on M-mode firmware that handles this for us transparently. As this patch breaks Linux bootup on all C9xx machines with MAEE, which don't have M-mode firmware that handles the access to the TH_MXSTATUS CSR, this patch is marked as RFC. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- arch/riscv/errata/thead/errata.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 8c8a8a4b0421..dd7bf6c62a35 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,6 +19,9 @@ #include <asm/patch.h> #include <asm/vendorid_list.h> +#define CSR_TH_MXSTATUS 0x7c0 +#define MXSTATUS_MAEE _AC(0x200000, UL) + static bool errata_probe_maee(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -28,11 +31,14 @@ static bool errata_probe_maee(unsigned int stage, if (arch_id != 0 || impid != 0) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || - stage == RISCV_ALTERNATIVES_MODULE) - return true; + if (stage != RISCV_ALTERNATIVES_EARLY_BOOT && + stage != RISCV_ALTERNATIVES_MODULE) + return false; - return false; + if (!(csr_read(CSR_TH_MXSTATUS) & MXSTATUS_MAEE)) + return false; + + return true; } /* -- 2.44.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-27 10:31 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-27 10:31 [PATCH 0/2] RISC-V: Test th.mxstatus.MAEE bit before enabling MAEE Christoph Müllner 2024-03-27 10:31 ` Christoph Müllner 2024-03-27 10:31 ` [PATCH 1/2] riscv: thead: Rename T-Head PBMT to MAEE Christoph Müllner 2024-03-27 10:31 ` Christoph Müllner 2024-03-27 10:31 ` Christoph Müllner [this message] 2024-03-27 10:31 ` [PATCH 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata Christoph Müllner 2024-03-27 11:03 ` Conor Dooley 2024-03-27 11:03 ` Conor Dooley 2024-03-27 12:41 ` Andrew Jones 2024-03-27 12:41 ` Andrew Jones 2024-03-28 14:18 ` Christoph Müllner 2024-03-28 14:18 ` Christoph Müllner 2024-03-28 14:57 ` Conor Dooley 2024-03-28 14:57 ` Conor Dooley 2024-03-28 15:43 ` Alexandre Ghiti 2024-03-28 15:43 ` Alexandre Ghiti 2024-03-29 11:22 ` Christoph Müllner 2024-03-29 11:22 ` Christoph Müllner 2024-03-29 11:29 ` Conor Dooley 2024-03-29 11:29 ` Conor Dooley 2024-03-27 12:59 ` [PATCH 0/2] RISC-V: Test th.mxstatus.MAEE bit before enabling MAEE Qingfang Deng 2024-03-27 12:59 ` Qingfang Deng 2024-03-28 14:19 ` Christoph Müllner 2024-03-28 14:19 ` Christoph Müllner
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