From: Alexander Usyskin <alexander.usyskin@intel.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Alexander Usyskin <alexander.usyskin@intel.com>, Vitaly Lubart <vitaly.lubart@intel.com>, linux-mtd@lists.infradead.org, intel-gfx@lists.freedesktop.org Subject: [PATCH 10/13] spi: intel-dg: align 64bit read and write Date: Thu, 28 Mar 2024 14:22:33 +0200 [thread overview] Message-ID: <20240328122236.1718111-11-alexander.usyskin@intel.com> (raw) In-Reply-To: <20240328122236.1718111-1-alexander.usyskin@intel.com> GSC SPI HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> --- drivers/spi/spi-intel-dg.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index 9e8be7713f1a..d626e9526631 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -231,6 +231,24 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region, len_s -= to_shift; } + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + spi_write32(spi, to, data); + if (spi_error(spi)) + return -EIO; + buf += sizeof(u32); + to += sizeof(u32); + len_s -= sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data; @@ -289,6 +307,23 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region, from += from_shift; } + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data = spi_read32(spi, from); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -= sizeof(u32); + buf += sizeof(u32); + from += sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data = spi_read64(spi, from + i); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexander Usyskin <alexander.usyskin@intel.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Alexander Usyskin <alexander.usyskin@intel.com>, Vitaly Lubart <vitaly.lubart@intel.com>, linux-mtd@lists.infradead.org, intel-gfx@lists.freedesktop.org Subject: [PATCH 10/13] spi: intel-dg: align 64bit read and write Date: Thu, 28 Mar 2024 14:22:33 +0200 [thread overview] Message-ID: <20240328122236.1718111-11-alexander.usyskin@intel.com> (raw) In-Reply-To: <20240328122236.1718111-1-alexander.usyskin@intel.com> GSC SPI HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> --- drivers/spi/spi-intel-dg.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index 9e8be7713f1a..d626e9526631 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -231,6 +231,24 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region, len_s -= to_shift; } + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + spi_write32(spi, to, data); + if (spi_error(spi)) + return -EIO; + buf += sizeof(u32); + to += sizeof(u32); + len_s -= sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data; @@ -289,6 +307,23 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region, from += from_shift; } + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data = spi_read32(spi, from); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -= sizeof(u32); + buf += sizeof(u32); + from += sizeof(u32); + } + len8 = ALIGN_DOWN(len_s, sizeof(u64)); for (i = 0; i < len8; i += sizeof(u64)) { u64 data = spi_read64(spi, from + i); -- 2.34.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2024-03-28 12:26 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-28 12:22 [PATCH 00/13] spi: add driver for Intel discrete graphics Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 01/13] spi: add auxiliary device for intel dg spi Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-29 12:46 ` Krzysztof Kozlowski 2024-04-11 13:43 ` Usyskin, Alexander 2024-04-11 13:43 ` Usyskin, Alexander 2024-04-11 13:51 ` Krzysztof Kozlowski 2024-03-28 12:22 ` [PATCH 02/13] drm/i915/spi: add spi device for discrete graphics Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 03/13] drm/i915/spi: add intel_spi_region map Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 04/13] drm/i915/spi: add support for access mode Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 05/13] spi: add driver for intel graphics on-die spi device Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-29 12:43 ` Krzysztof Kozlowski 2024-04-25 11:58 ` Usyskin, Alexander 2024-04-25 11:58 ` Usyskin, Alexander 2024-03-29 14:11 ` Lucas De Marchi 2024-03-29 14:11 ` Lucas De Marchi 2024-03-28 12:22 ` [PATCH 06/13] spi: intel-dg: implement region enumeration Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 07/13] spi: intel-dg: implement spi access functions Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 08/13] spi: intel-dg: spi register with mtd Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 09/13] spi: intel-dg: implement mtd access handlers Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin [this message] 2024-03-28 12:22 ` [PATCH 10/13] spi: intel-dg: align 64bit read and write Alexander Usyskin 2024-03-28 12:22 ` [PATCH 11/13] spi: intel-dg: wake card on operations Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-28 12:22 ` [PATCH 12/13] drm/xe/spi: add on-die spi device Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-29 12:46 ` Krzysztof Kozlowski 2024-03-28 12:22 ` [PATCH 13/13] drm/xe/spi: add support for access mode Alexander Usyskin 2024-03-28 12:22 ` Alexander Usyskin 2024-03-29 1:15 ` ✗ Fi.CI.BUILD: failure for spi: add driver for Intel discrete graphics Patchwork
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