From: Max Hsu <max.hsu@sifive.com> To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J. Wysocki" <rafael@kernel.org>, Pavel Machek <pavel@ucw.cz>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Paolo Bonzini <pbonzini@redhat.com>, Shuah Khan <shuah@kernel.org> Cc: Palmer Dabbelt <palmer@sifive.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu <max.hsu@sifive.com> Subject: [PATCH RFC 03/11] riscv: Add ISA extension parsing for Sdtrig Date: Fri, 29 Mar 2024 17:26:19 +0800 [thread overview] Message-ID: <20240329-dev-maxh-lin-452-6-9-v1-3-1534f93b94a7@sifive.com> (raw) In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> Add ISA extension parsing for Sdtrig as introduced in riscv-debug-spec [1] Chapter 5 Link: https://github.com/riscv/riscv-debug-spec/releases/download/ar20231208/riscv-debug-stable.pdf [1] Signed-off-by: Max Hsu <max.hsu@sifive.com> --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..9f8d780fce35 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SDTRIG 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..080c06b76f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -296,6 +296,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_DATA(sdtrig, RISCV_ISA_EXT_SDTRIG), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), -- 2.43.2
WARNING: multiple messages have this Message-ID (diff)
From: Max Hsu <max.hsu@sifive.com> To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J. Wysocki" <rafael@kernel.org>, Pavel Machek <pavel@ucw.cz>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Paolo Bonzini <pbonzini@redhat.com>, Shuah Khan <shuah@kernel.org> Cc: Palmer Dabbelt <palmer@sifive.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu <max.hsu@sifive.com> Subject: [PATCH RFC 03/11] riscv: Add ISA extension parsing for Sdtrig Date: Fri, 29 Mar 2024 17:26:19 +0800 [thread overview] Message-ID: <20240329-dev-maxh-lin-452-6-9-v1-3-1534f93b94a7@sifive.com> (raw) In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> Add ISA extension parsing for Sdtrig as introduced in riscv-debug-spec [1] Chapter 5 Link: https://github.com/riscv/riscv-debug-spec/releases/download/ar20231208/riscv-debug-stable.pdf [1] Signed-off-by: Max Hsu <max.hsu@sifive.com> --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..9f8d780fce35 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SDTRIG 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..080c06b76f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -296,6 +296,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_DATA(sdtrig, RISCV_ISA_EXT_SDTRIG), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), -- 2.43.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-29 9:27 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-29 9:26 [PATCH RFC 00/11] riscv: support Sdtrig extension hcontext/scontext CSRs Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 01/11] dt-bindings: riscv: Add Sdtrig ISA extension Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 02/11] dt-bindings: riscv: Add Sdtrig optional CSRs existence on DT Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 10:31 ` Conor Dooley 2024-03-29 10:31 ` Conor Dooley 2024-04-05 15:59 ` Andrew Jones 2024-04-05 15:59 ` Andrew Jones 2024-04-09 15:49 ` Conor Dooley 2024-04-09 15:49 ` Conor Dooley 2024-03-29 9:26 ` Max Hsu [this message] 2024-03-29 9:26 ` [PATCH RFC 03/11] riscv: Add ISA extension parsing for Sdtrig Max Hsu 2024-03-29 9:26 ` [PATCH RFC 04/11] riscv: Add Sdtrig CSRs definition, Smstateen bit to access Sdtrig CSRs Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 05/11] riscv: cpufeature: Add Sdtrig optional CSRs checks Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 10:21 ` Conor Dooley 2024-03-29 10:21 ` Conor Dooley 2024-03-29 9:26 ` [PATCH RFC 06/11] riscv: suspend: add Smstateen CSRs save/restore Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 07/11] riscv: Add task switch support for scontext CSR Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 08/11] riscv: KVM: Add Sdtrig Extension Support for Guest/VM Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 09/11] riscv: KVM: Add scontext to ONE_REG Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 10/11] riscv: KVM: Add hcontext support Max Hsu 2024-03-29 9:26 ` Max Hsu 2024-03-29 9:26 ` [PATCH RFC 11/11] KVM: riscv: selftests: Add Sdtrig Extension to get-reg-list test Max Hsu 2024-03-29 9:26 ` Max Hsu
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