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From: Max Hsu <max.hsu@sifive.com>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 "Rafael J. Wysocki" <rafael@kernel.org>,
	Pavel Machek <pavel@ucw.cz>,  Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	 Paolo Bonzini <pbonzini@redhat.com>,
	Shuah Khan <shuah@kernel.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
	linux-riscv@lists.infradead.org,  devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,  linux-pm@vger.kernel.org,
	kvm@vger.kernel.org,  kvm-riscv@lists.infradead.org,
	linux-kselftest@vger.kernel.org,  Max Hsu <max.hsu@sifive.com>
Subject: [PATCH RFC 04/11] riscv: Add Sdtrig CSRs definition, Smstateen bit to access Sdtrig CSRs
Date: Fri, 29 Mar 2024 17:26:20 +0800	[thread overview]
Message-ID: <20240329-dev-maxh-lin-452-6-9-v1-4-1534f93b94a7@sifive.com> (raw)
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>

Add hcontext/scontext CSRs definition to csr.h

As riscv-state-enable [1] Smstateen extension spec:
Sdtrig CSRs: hcontext/scontext availability are controlled by
bit 57 of Smstateen CSRs.

Link: https://github.com/riscvarchive/riscv-state-enable/releases/download/v1.0.0/Smstateen.pdf [1]
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
 arch/riscv/include/asm/csr.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..308ae795dc82 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -204,6 +204,8 @@
 #define ENVCFG_FIOM			_AC(0x1, UL)
 
 /* Smstateen bits */
+#define SMSTATEEN0_HSCONTEXT_SHIFT	57
+#define SMSTATEEN0_HSCONTEXT		(_ULL(1) << SMSTATEEN0_HSCONTEXT_SHIFT)
 #define SMSTATEEN0_AIA_IMSIC_SHIFT	58
 #define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
 #define SMSTATEEN0_AIA_SHIFT		59
@@ -480,6 +482,10 @@
 #define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
 #define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
 
+/* riscv-debug-spec: Sdtrig extension */
+#define CSR_SCONTEXT	0x5a8
+#define CSR_HCONTEXT	0x6a8
+
 #ifndef __ASSEMBLY__
 
 #define csr_swap(csr, val)					\

-- 
2.43.2


WARNING: multiple messages have this Message-ID (diff)
From: Max Hsu <max.hsu@sifive.com>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 "Rafael J. Wysocki" <rafael@kernel.org>,
	Pavel Machek <pavel@ucw.cz>,  Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	 Paolo Bonzini <pbonzini@redhat.com>,
	Shuah Khan <shuah@kernel.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
	linux-riscv@lists.infradead.org,  devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,  linux-pm@vger.kernel.org,
	kvm@vger.kernel.org,  kvm-riscv@lists.infradead.org,
	linux-kselftest@vger.kernel.org,  Max Hsu <max.hsu@sifive.com>
Subject: [PATCH RFC 04/11] riscv: Add Sdtrig CSRs definition, Smstateen bit to access Sdtrig CSRs
Date: Fri, 29 Mar 2024 17:26:20 +0800	[thread overview]
Message-ID: <20240329-dev-maxh-lin-452-6-9-v1-4-1534f93b94a7@sifive.com> (raw)
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>

Add hcontext/scontext CSRs definition to csr.h

As riscv-state-enable [1] Smstateen extension spec:
Sdtrig CSRs: hcontext/scontext availability are controlled by
bit 57 of Smstateen CSRs.

Link: https://github.com/riscvarchive/riscv-state-enable/releases/download/v1.0.0/Smstateen.pdf [1]
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
 arch/riscv/include/asm/csr.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..308ae795dc82 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -204,6 +204,8 @@
 #define ENVCFG_FIOM			_AC(0x1, UL)
 
 /* Smstateen bits */
+#define SMSTATEEN0_HSCONTEXT_SHIFT	57
+#define SMSTATEEN0_HSCONTEXT		(_ULL(1) << SMSTATEEN0_HSCONTEXT_SHIFT)
 #define SMSTATEEN0_AIA_IMSIC_SHIFT	58
 #define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
 #define SMSTATEEN0_AIA_SHIFT		59
@@ -480,6 +482,10 @@
 #define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
 #define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
 
+/* riscv-debug-spec: Sdtrig extension */
+#define CSR_SCONTEXT	0x5a8
+#define CSR_HCONTEXT	0x6a8
+
 #ifndef __ASSEMBLY__
 
 #define csr_swap(csr, val)					\

-- 
2.43.2


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  parent reply	other threads:[~2024-03-29  9:27 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-29  9:26 [PATCH RFC 00/11] riscv: support Sdtrig extension hcontext/scontext CSRs Max Hsu
2024-03-29  9:26 ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 01/11] dt-bindings: riscv: Add Sdtrig ISA extension Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 02/11] dt-bindings: riscv: Add Sdtrig optional CSRs existence on DT Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29 10:31   ` Conor Dooley
2024-03-29 10:31     ` Conor Dooley
2024-04-05 15:59     ` Andrew Jones
2024-04-05 15:59       ` Andrew Jones
2024-04-09 15:49       ` Conor Dooley
2024-04-09 15:49         ` Conor Dooley
2024-03-29  9:26 ` [PATCH RFC 03/11] riscv: Add ISA extension parsing for Sdtrig Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` Max Hsu [this message]
2024-03-29  9:26   ` [PATCH RFC 04/11] riscv: Add Sdtrig CSRs definition, Smstateen bit to access Sdtrig CSRs Max Hsu
2024-03-29  9:26 ` [PATCH RFC 05/11] riscv: cpufeature: Add Sdtrig optional CSRs checks Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29 10:21   ` Conor Dooley
2024-03-29 10:21     ` Conor Dooley
2024-03-29  9:26 ` [PATCH RFC 06/11] riscv: suspend: add Smstateen CSRs save/restore Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 07/11] riscv: Add task switch support for scontext CSR Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 08/11] riscv: KVM: Add Sdtrig Extension Support for Guest/VM Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 09/11] riscv: KVM: Add scontext to ONE_REG Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 10/11] riscv: KVM: Add hcontext support Max Hsu
2024-03-29  9:26   ` Max Hsu
2024-03-29  9:26 ` [PATCH RFC 11/11] KVM: riscv: selftests: Add Sdtrig Extension to get-reg-list test Max Hsu
2024-03-29  9:26   ` Max Hsu

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