From: Deepak Gupta <debug@rivosinc.com> To: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, tech-j-ext@lists.risc-v.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, charlie@rivosinc.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: [PATCH v2 16/27] prctl: arch-agnostic prtcl for indirect branch tracking Date: Thu, 28 Mar 2024 21:44:48 -0700 [thread overview] Message-ID: <20240329044459.3990638-17-debug@rivosinc.com> (raw) In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com> Three architectures (x86, aarch64, riscv) have support for indirect branch tracking feature in a very similar fashion. On a very high level, indirect branch tracking is a CPU feature where CPU tracks branches which uses memory operand to perform control transfer in program. As part of this tracking on indirect branches, CPU goes in a state where it expects a landing pad instr on target and if not found then CPU raises some fault (architecture dependent) x86 landing pad instr - `ENDBRANCH` aarch64 landing pad instr - `BTI` riscv landing instr - `lpad` Given that three major arches have support for indirect branch tracking, This patch makes `prctl` for indirect branch tracking arch agnostic. To allow userspace to enable this feature for itself, following prtcls are defined: - PR_GET_INDIR_BR_LP_STATUS: Gets current configured status for indirect branch tracking. - PR_SET_INDIR_BR_LP_STATUS: Sets a configuration for indirect branch tracking Following status options are allowed - PR_INDIR_BR_LP_ENABLE: Enables indirect branch tracking on user thread. - PR_INDIR_BR_LP_DISABLE; Disables indirect branch tracking on user thread. - PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch tracking for user thread. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- include/uapi/linux/prctl.h | 27 +++++++++++++++++++++++++++ kernel/sys.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 3c66ed8f46d8..b7a8212a068e 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -328,4 +328,31 @@ struct prctl_mm_map { */ #define PR_LOCK_SHADOW_STACK_STATUS 73 +/* + * Get the current indirect branch tracking configuration for the current + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS. + */ +#define PR_GET_INDIR_BR_LP_STATUS 74 + +/* + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will + * enable cpu feature for user thread, to track all indirect branches and ensure + * they land on arch defined landing pad instruction. + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction. + * arch64 - If enabled, an indirect branch must land on `BTI` instruction. + * riscv - If enabled, an indirect branch must land on `lpad` instruction. + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect + * branches will no more be tracked by cpu to land on arch defined landing pad + * instruction. + */ +#define PR_SET_INDIR_BR_LP_STATUS 75 +# define PR_INDIR_BR_LP_ENABLE (1UL << 0) + +/* + * Prevent further changes to the specified indirect branch tracking + * configuration. All bits may be locked via this call, including + * undefined bits. + */ +#define PR_LOCK_INDIR_BR_LP_STATUS 76 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 242e9f147791..c770060c3f06 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2330,6 +2330,21 @@ int __weak arch_lock_shadow_stack_status(struct task_struct *t, unsigned long st return -EINVAL; } +int __weak arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) +{ + return -EINVAL; +} + +int __weak arch_set_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) +{ + return -EINVAL; +} + +int __weak arch_lock_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) +{ + return -EINVAL; +} + #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE) #ifdef CONFIG_ANON_VMA_NAME @@ -2787,6 +2802,21 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, return -EINVAL; error = arch_lock_shadow_stack_status(me, arg2); break; + case PR_GET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error = arch_get_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; + case PR_SET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error = arch_set_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; + case PR_LOCK_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error = arch_lock_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; default: error = -EINVAL; break; -- 2.43.2
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com> To: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, tech-j-ext@lists.risc-v.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, charlie@rivosinc.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: [PATCH v2 16/27] prctl: arch-agnostic prtcl for indirect branch tracking Date: Thu, 28 Mar 2024 21:44:48 -0700 [thread overview] Message-ID: <20240329044459.3990638-17-debug@rivosinc.com> (raw) In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com> Three architectures (x86, aarch64, riscv) have support for indirect branch tracking feature in a very similar fashion. On a very high level, indirect branch tracking is a CPU feature where CPU tracks branches which uses memory operand to perform control transfer in program. As part of this tracking on indirect branches, CPU goes in a state where it expects a landing pad instr on target and if not found then CPU raises some fault (architecture dependent) x86 landing pad instr - `ENDBRANCH` aarch64 landing pad instr - `BTI` riscv landing instr - `lpad` Given that three major arches have support for indirect branch tracking, This patch makes `prctl` for indirect branch tracking arch agnostic. To allow userspace to enable this feature for itself, following prtcls are defined: - PR_GET_INDIR_BR_LP_STATUS: Gets current configured status for indirect branch tracking. - PR_SET_INDIR_BR_LP_STATUS: Sets a configuration for indirect branch tracking Following status options are allowed - PR_INDIR_BR_LP_ENABLE: Enables indirect branch tracking on user thread. - PR_INDIR_BR_LP_DISABLE; Disables indirect branch tracking on user thread. - PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch tracking for user thread. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- include/uapi/linux/prctl.h | 27 +++++++++++++++++++++++++++ kernel/sys.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 3c66ed8f46d8..b7a8212a068e 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -328,4 +328,31 @@ struct prctl_mm_map { */ #define PR_LOCK_SHADOW_STACK_STATUS 73 +/* + * Get the current indirect branch tracking configuration for the current + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS. + */ +#define PR_GET_INDIR_BR_LP_STATUS 74 + +/* + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will + * enable cpu feature for user thread, to track all indirect branches and ensure + * they land on arch defined landing pad instruction. + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction. + * arch64 - If enabled, an indirect branch must land on `BTI` instruction. + * riscv - If enabled, an indirect branch must land on `lpad` instruction. + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect + * branches will no more be tracked by cpu to land on arch defined landing pad + * instruction. + */ +#define PR_SET_INDIR_BR_LP_STATUS 75 +# define PR_INDIR_BR_LP_ENABLE (1UL << 0) + +/* + * Prevent further changes to the specified indirect branch tracking + * configuration. All bits may be locked via this call, including + * undefined bits. + */ +#define PR_LOCK_INDIR_BR_LP_STATUS 76 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 242e9f147791..c770060c3f06 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2330,6 +2330,21 @@ int __weak arch_lock_shadow_stack_status(struct task_struct *t, unsigned long st return -EINVAL; } +int __weak arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) +{ + return -EINVAL; +} + +int __weak arch_set_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) +{ + return -EINVAL; +} + +int __weak arch_lock_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) +{ + return -EINVAL; +} + #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE) #ifdef CONFIG_ANON_VMA_NAME @@ -2787,6 +2802,21 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, return -EINVAL; error = arch_lock_shadow_stack_status(me, arg2); break; + case PR_GET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error = arch_get_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; + case PR_SET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error = arch_set_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; + case PR_LOCK_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error = arch_lock_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; default: error = -EINVAL; break; -- 2.43.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-29 4:46 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-29 4:44 [PATCH v2 00/27] riscv control-flow integrity for usermode Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 01/27] riscv: envcfg save and restore on task switching Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 02/27] riscv: define default value for envcfg Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 03/27] riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 5:08 ` Stefan O'Rear 2024-03-29 5:08 ` Stefan O'Rear 2024-03-29 5:13 ` Deepak Gupta 2024-03-29 5:13 ` Deepak Gupta 2024-03-29 7:24 ` Conor Dooley 2024-03-29 7:24 ` Conor Dooley 2024-03-29 4:44 ` [PATCH v2 05/27] riscv: zicfiss/zicfilp extension csr and bit definitions Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 06/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 07/27] mm: Define VM_SHADOW_STACK for RISC-V Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 08/27] mm: abstract shadow stack vma behind `arch_is_shadow_stack` Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 09/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 10/27] riscv mm: manufacture shadow stack pte Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 11/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 5:15 ` Deepak Gupta 2024-03-29 5:15 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 12/27] riscv mmu: write protect and shadow stack Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 13/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 14/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 15/27] prctl: arch-agnostic prctl for shadow stack Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta [this message] 2024-03-29 4:44 ` [PATCH v2 16/27] prctl: arch-agnostic prtcl for indirect branch tracking Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 17/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 18/27] riscv: Implements arch argnostic indirect branch tracking prctls Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 19/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 20/27] riscv/traps: Introduce software check exception Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 21/27] riscv sigcontext: adding cfi state field in sigcontext Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 22/27] riscv signal: Save and restore of shadow stack for signal Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 23/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 19:50 ` Muhammad Usama Anjum 2024-03-29 19:50 ` Muhammad Usama Anjum 2024-03-29 20:02 ` Deepak Gupta 2024-03-29 20:02 ` Deepak Gupta 2024-04-01 9:46 ` Muhammad Usama Anjum 2024-04-01 9:46 ` Muhammad Usama Anjum 2024-04-01 17:34 ` Deepak Gupta 2024-04-01 17:34 ` Deepak Gupta 2024-04-01 17:55 ` Deepak Gupta 2024-04-01 17:55 ` Deepak Gupta
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