From: Deepak Gupta <debug@rivosinc.com> To: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, tech-j-ext@lists.risc-v.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, charlie@rivosinc.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration Date: Thu, 28 Mar 2024 21:44:36 -0700 [thread overview] Message-ID: <20240329044459.3990638-5-debug@rivosinc.com> (raw) In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com> Adds description in dt-bindings (extensions.yaml) This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature bitmap. Furthermore this patch adds detection utility functions to return whether shadow stack or landing pads are supported by cpu. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- .../devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ 5 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..f8d78bf7400b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -317,6 +317,16 @@ properties: The standard Zicboz extension for cache-block zeroing as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: zicfilp + description: + The standard Zicfilp extension for enforcing forward edge control-flow + integrity as ratified in commit 0036ff2 of riscv-cfi. + + - const: zicfiss + description: + The standard Zicfiss extension for enforcing backward edge control-flow + integrity as ratified in commit 0036ff2 of riscv-cfi. + - const: zicntr description: The standard Zicntr extension for base counters and timers, as diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 0bd11862b760..f0fb8d8ae273 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -8,6 +8,7 @@ #include <linux/bitmap.h> #include <linux/jump_label.h> +#include <linux/smp.h> #include <asm/hwcap.h> #include <asm/alternative-macros.h> #include <asm/errno.h> @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); +static inline bool cpu_supports_shadow_stack(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); +} + +static inline bool cpu_supports_indirect_br_lp_instr(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 1f2d2599c655..74b6c727f545 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,8 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_ZICFILP 74 +#define RISCV_ISA_EXT_ZICFISS 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index a8509cc31ab2..6c5b3d928b12 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -13,6 +13,7 @@ #include <vdso/processor.h> #include <asm/ptrace.h> +#include <asm/hwcap.h> #ifdef CONFIG_64BIT #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 79a5a35fab96..d052cad5b82f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), -- 2.43.2
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com> To: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, tech-j-ext@lists.risc-v.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, charlie@rivosinc.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration Date: Thu, 28 Mar 2024 21:44:36 -0700 [thread overview] Message-ID: <20240329044459.3990638-5-debug@rivosinc.com> (raw) In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com> Adds description in dt-bindings (extensions.yaml) This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature bitmap. Furthermore this patch adds detection utility functions to return whether shadow stack or landing pads are supported by cpu. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- .../devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ 5 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..f8d78bf7400b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -317,6 +317,16 @@ properties: The standard Zicboz extension for cache-block zeroing as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: zicfilp + description: + The standard Zicfilp extension for enforcing forward edge control-flow + integrity as ratified in commit 0036ff2 of riscv-cfi. + + - const: zicfiss + description: + The standard Zicfiss extension for enforcing backward edge control-flow + integrity as ratified in commit 0036ff2 of riscv-cfi. + - const: zicntr description: The standard Zicntr extension for base counters and timers, as diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 0bd11862b760..f0fb8d8ae273 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -8,6 +8,7 @@ #include <linux/bitmap.h> #include <linux/jump_label.h> +#include <linux/smp.h> #include <asm/hwcap.h> #include <asm/alternative-macros.h> #include <asm/errno.h> @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); +static inline bool cpu_supports_shadow_stack(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); +} + +static inline bool cpu_supports_indirect_br_lp_instr(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 1f2d2599c655..74b6c727f545 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,8 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_ZICFILP 74 +#define RISCV_ISA_EXT_ZICFISS 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index a8509cc31ab2..6c5b3d928b12 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -13,6 +13,7 @@ #include <vdso/processor.h> #include <asm/ptrace.h> +#include <asm/hwcap.h> #ifdef CONFIG_64BIT #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 79a5a35fab96..d052cad5b82f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), -- 2.43.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-29 4:46 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-29 4:44 [PATCH v2 00/27] riscv control-flow integrity for usermode Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 01/27] riscv: envcfg save and restore on task switching Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 02/27] riscv: define default value for envcfg Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 03/27] riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta [this message] 2024-03-29 4:44 ` [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration Deepak Gupta 2024-03-29 5:08 ` Stefan O'Rear 2024-03-29 5:08 ` Stefan O'Rear 2024-03-29 5:13 ` Deepak Gupta 2024-03-29 5:13 ` Deepak Gupta 2024-03-29 7:24 ` Conor Dooley 2024-03-29 7:24 ` Conor Dooley 2024-03-29 4:44 ` [PATCH v2 05/27] riscv: zicfiss/zicfilp extension csr and bit definitions Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 06/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 07/27] mm: Define VM_SHADOW_STACK for RISC-V Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 08/27] mm: abstract shadow stack vma behind `arch_is_shadow_stack` Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 09/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 10/27] riscv mm: manufacture shadow stack pte Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 11/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 5:15 ` Deepak Gupta 2024-03-29 5:15 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 12/27] riscv mmu: write protect and shadow stack Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 13/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 14/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 15/27] prctl: arch-agnostic prctl for shadow stack Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 16/27] prctl: arch-agnostic prtcl for indirect branch tracking Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 17/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 18/27] riscv: Implements arch argnostic indirect branch tracking prctls Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 19/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 20/27] riscv/traps: Introduce software check exception Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 21/27] riscv sigcontext: adding cfi state field in sigcontext Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 22/27] riscv signal: Save and restore of shadow stack for signal Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 23/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 4:44 ` [PATCH v2 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta 2024-03-29 4:44 ` Deepak Gupta 2024-03-29 19:50 ` Muhammad Usama Anjum 2024-03-29 19:50 ` Muhammad Usama Anjum 2024-03-29 20:02 ` Deepak Gupta 2024-03-29 20:02 ` Deepak Gupta 2024-04-01 9:46 ` Muhammad Usama Anjum 2024-04-01 9:46 ` Muhammad Usama Anjum 2024-04-01 17:34 ` Deepak Gupta 2024-04-01 17:34 ` Deepak Gupta 2024-04-01 17:55 ` Deepak Gupta 2024-04-01 17:55 ` Deepak Gupta
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