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From: Akhil R <akhilrajeev@nvidia.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
	<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <catalin.marinas@arm.com>,
	<will@kernel.org>, <mperttunen@nvidia.com>, <airlied@gmail.com>,
	<daniel@ffwll.ch>, <linux-crypto@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<dri-devel@lists.freedesktop.org>
Cc: Akhil R <akhilrajeev@nvidia.com>
Subject: [PATCH v7 2/5] gpu: host1x: Add Tegra SE to SID table
Date: Wed, 3 Apr 2024 15:30:36 +0530	[thread overview]
Message-ID: <20240403100039.33146-3-akhilrajeev@nvidia.com> (raw)
In-Reply-To: <20240403100039.33146-1-akhilrajeev@nvidia.com>

Add Tegra Security Engine details to the SID table in host1x driver.
These entries are required to be in place to configure the stream ID
for SE. Register writes to stream ID registers fail otherwise.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 89983d7d73ca..3a0aaa68ac8d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -215,6 +215,30 @@ static const struct host1x_info host1x07_info = {
  * and firmware stream ID in the MMIO path table.
  */
 static const struct host1x_sid_entry tegra234_sid_table[] = {
+	{
+		/* SE2 MMIO */
+		.base = 0x1658,
+		.offset = 0x90,
+		.limit = 0x90
+	},
+	{
+		/* SE4 MMIO */
+		.base = 0x1660,
+		.offset = 0x90,
+		.limit = 0x90
+	},
+	{
+		/* SE2 channel */
+		.base = 0x1738,
+		.offset = 0x90,
+		.limit = 0x90
+	},
+	{
+		/* SE4 channel */
+		.base = 0x1740,
+		.offset = 0x90,
+		.limit = 0x90
+	},
 	{
 		/* VIC channel */
 		.base = 0x17b8,
-- 
2.43.2


WARNING: multiple messages have this Message-ID (diff)
From: Akhil R <akhilrajeev@nvidia.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
	<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <catalin.marinas@arm.com>,
	<will@kernel.org>, <mperttunen@nvidia.com>, <airlied@gmail.com>,
	<daniel@ffwll.ch>, <linux-crypto@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<dri-devel@lists.freedesktop.org>
Cc: Akhil R <akhilrajeev@nvidia.com>
Subject: [PATCH v7 2/5] gpu: host1x: Add Tegra SE to SID table
Date: Wed, 3 Apr 2024 15:30:36 +0530	[thread overview]
Message-ID: <20240403100039.33146-3-akhilrajeev@nvidia.com> (raw)
In-Reply-To: <20240403100039.33146-1-akhilrajeev@nvidia.com>

Add Tegra Security Engine details to the SID table in host1x driver.
These entries are required to be in place to configure the stream ID
for SE. Register writes to stream ID registers fail otherwise.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 89983d7d73ca..3a0aaa68ac8d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -215,6 +215,30 @@ static const struct host1x_info host1x07_info = {
  * and firmware stream ID in the MMIO path table.
  */
 static const struct host1x_sid_entry tegra234_sid_table[] = {
+	{
+		/* SE2 MMIO */
+		.base = 0x1658,
+		.offset = 0x90,
+		.limit = 0x90
+	},
+	{
+		/* SE4 MMIO */
+		.base = 0x1660,
+		.offset = 0x90,
+		.limit = 0x90
+	},
+	{
+		/* SE2 channel */
+		.base = 0x1738,
+		.offset = 0x90,
+		.limit = 0x90
+	},
+	{
+		/* SE4 channel */
+		.base = 0x1740,
+		.offset = 0x90,
+		.limit = 0x90
+	},
 	{
 		/* VIC channel */
 		.base = 0x17b8,
-- 
2.43.2


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  parent reply	other threads:[~2024-04-03 10:02 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
2024-04-03 10:00 ` Akhil R
2024-04-03 10:00 ` [PATCH v7 1/5] dt-bindings: crypto: Add Tegra Security Engine Akhil R
2024-04-03 10:00   ` Akhil R
2024-04-03 10:00 ` Akhil R [this message]
2024-04-03 10:00   ` [PATCH v7 2/5] gpu: host1x: Add Tegra SE to SID table Akhil R
2024-04-03 10:00 ` [PATCH v7 3/5] crypto: tegra: Add Tegra Security Engine driver Akhil R
2024-04-03 10:00 ` [PATCH v7 4/5] arm64: defconfig: Enable Tegra Security Engine Akhil R
2024-04-03 10:00   ` Akhil R
2024-04-03 10:00 ` [PATCH v7 5/5] arm64: tegra: Add Tegra Security Engine DT nodes Akhil R
2024-04-03 10:00   ` Akhil R
2024-04-12  7:31 ` [PATCH v7 0/5] Add Tegra Security Engine driver Herbert Xu
2024-04-12  7:31   ` Herbert Xu
2024-05-01  4:52   ` Akhil R
2024-05-01  8:05     ` Herbert Xu
2024-05-02 14:56       ` Akhil R
2024-05-03  9:15         ` Jon Hunter
2024-05-03 10:00         ` Herbert Xu
2024-05-07  3:43           ` Akhil R
2024-04-26 15:32 ` (subset) " Thierry Reding
2024-04-26 15:32   ` Thierry Reding
2024-04-26 15:35   ` Thierry Reding
2024-04-26 15:35     ` Thierry Reding

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