From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Clint Taylor <Clinton.A.Taylor@intel.com>
Subject: [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address
Date: Wed, 3 Apr 2024 16:52:29 +0530 [thread overview]
Message-ID: <20240403112253.1432390-2-balasubramani.vivekanandan@intel.com> (raw)
In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com>
New platforms have different addresses for C20 PLL registers. This patch
prepares the driver to work with different register addresses.
New structure `struct intel_c20pll_reg` is created to hold the register
addresses for each platform with different register address.
CC: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +++++++++++++------
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++++++++++---
2 files changed, 65 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a2c4bf33155f..13a2e3db2812 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -759,6 +759,17 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
NULL,
};
+static struct intel_c20pll_reg mtl_c20_reg = {
+ .tx_cnt_a = MTL_C20_A_TX_CNTX_CFG_ADDR,
+ .tx_cnt_b = MTL_C20_B_TX_CNTX_CFG_ADDR,
+ .cmn_cnt_a = MTL_C20_A_CMN_CNTX_CFG_ADDR,
+ .cmn_cnt_b = MTL_C20_B_CMN_CNTX_CFG_ADDR,
+ .mplla_a = MTL_C20_A_MPLLA_CFG_ADDR,
+ .mplla_b = MTL_C20_B_MPLLA_CFG_ADDR,
+ .mpllb_a = MTL_C20_A_MPLLB_CFG_ADDR,
+ .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
+};
+
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.clock = 162000,
@@ -2161,6 +2172,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
bool cntx;
intel_wakeref_t wakeref;
int i;
+ struct intel_c20pll_reg *pll_reg = &mtl_c20_reg;
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2171,20 +2183,20 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i));
+ PHY_C20_B_TX_CNTX_CFG(pll_reg, i));
else
pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i));
+ PHY_C20_A_TX_CNTX_CFG(pll_reg, i));
}
/* Read common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i));
+ PHY_C20_B_CMN_CNTX_CFG(pll_reg, i));
else
pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i));
+ PHY_C20_A_CMN_CNTX_CFG(pll_reg, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
@@ -2192,20 +2204,20 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i));
+ PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i));
else
pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i));
+ PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i));
}
} else {
/* MPLLA configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i));
+ PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i));
else
pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i));
+ PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i));
}
}
@@ -2341,6 +2353,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
u32 clock = crtc_state->port_clock;
bool cntx;
int i;
+ const struct intel_c20pll_reg *pll_reg = &mtl_c20_reg;
if (intel_crtc_has_dp_encoder(crtc_state))
dp = true;
@@ -2363,17 +2376,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
/* 3.1 Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_A_TX_CNTX_CFG(pll_reg, i),
+ pll_state->tx[i]);
else
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_B_TX_CNTX_CFG(pll_reg, i),
+ pll_state->tx[i]);
}
/* 3.2 common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_A_CMN_CNTX_CFG(pll_reg, i),
+ pll_state->cmn[i]);
else
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_B_CMN_CNTX_CFG(pll_reg, i),
+ pll_state->cmn[i]);
}
/* 3.3 mpllb or mplla configuration */
@@ -2381,22 +2402,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i),
+ PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i),
pll_state->mpllb[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i),
+ PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i),
pll_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i),
+ PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i),
pll_state->mplla[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i),
+ PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i),
pll_state->mplla[i]);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bdd0c8c4ef97..882b98dc347b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -254,24 +254,44 @@
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
-#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
-#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
+#define PHY_C20_A_TX_CNTX_CFG(reg, idx) ((reg)->tx_cnt_a - (idx))
+#define PHY_C20_B_TX_CNTX_CFG(reg, idx) ((reg)->tx_cnt_b - (idx))
#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
-#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
-#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
-#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
-#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
+#define PHY_C20_A_CMN_CNTX_CFG(reg, idx) ((reg)->cmn_cnt_a - (idx))
+#define PHY_C20_B_CMN_CNTX_CFG(reg, idx) ((reg)->cmn_cnt_b - (idx))
+#define PHY_C20_A_MPLLA_CNTX_CFG(reg, idx) ((reg)->mplla_a - (idx))
+#define PHY_C20_B_MPLLA_CNTX_CFG(reg, idx) ((reg)->mplla_b - (idx))
#define C20_MPLLA_FRACEN REG_BIT(14)
#define C20_FB_CLK_DIV4_EN REG_BIT(13)
#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
-#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
-#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
+#define PHY_C20_A_MPLLB_CNTX_CFG(reg, idx) ((reg)->mpllb_a - (idx))
+#define PHY_C20_B_MPLLB_CNTX_CFG(reg, idx) ((reg)->mpllb_b - (idx))
#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
#define C20_MPLLB_FRACEN REG_BIT(13)
#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
#define C20_PHY_USE_MPLLB REG_BIT(7)
+struct intel_c20pll_reg {
+ u16 tx_cnt_a;
+ u16 tx_cnt_b;
+ u16 cmn_cnt_a;
+ u16 cmn_cnt_b;
+ u16 mplla_a;
+ u16 mplla_b;
+ u16 mpllb_a;
+ u16 mpllb_b;
+};
+
+#define MTL_C20_A_TX_CNTX_CFG_ADDR 0xCF2E
+#define MTL_C20_B_TX_CNTX_CFG_ADDR 0xCF2A
+#define MTL_C20_A_CMN_CNTX_CFG_ADDR 0xCDAA
+#define MTL_C20_B_CMN_CNTX_CFG_ADDR 0xCDA5
+#define MTL_C20_A_MPLLA_CFG_ADDR 0xCCF0
+#define MTL_C20_B_MPLLA_CFG_ADDR 0xCCE5
+#define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A
+#define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E
+
/* C20 Phy VSwing Masks */
#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
--
2.25.1
next prev parent reply other threads:[~2024-04-03 11:22 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 11:22 [PATCH v2 00/25] Enable dislay support for Battlemage Balasubramani Vivekanandan
2024-04-03 11:22 ` Balasubramani Vivekanandan [this message]
2024-04-03 11:40 ` [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address Jani Nikula
2024-04-03 11:22 ` [PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition Balasubramani Vivekanandan
2024-04-03 13:16 ` Lucas De Marchi
2024-04-03 11:22 ` [PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro Balasubramani Vivekanandan
2024-04-03 18:05 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 04/25] drm/i915/bmg: " Balasubramani Vivekanandan
2024-04-03 18:11 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms Balasubramani Vivekanandan
2024-04-03 19:02 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table Balasubramani Vivekanandan
2024-04-03 19:05 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Balasubramani Vivekanandan
2024-04-03 19:14 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future Balasubramani Vivekanandan
2024-04-03 19:15 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A Balasubramani Vivekanandan
2024-04-03 19:28 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address Balasubramani Vivekanandan
2024-04-03 12:00 ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration Balasubramani Vivekanandan
2024-04-03 20:11 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec Balasubramani Vivekanandan
2024-04-03 20:41 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 13/25] drm/i915/xe2hpd: Add display info Balasubramani Vivekanandan
2024-04-03 21:12 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming Balasubramani Vivekanandan
2024-04-03 21:00 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes Balasubramani Vivekanandan
2024-04-03 11:52 ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR Balasubramani Vivekanandan
2024-04-03 11:53 ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm Balasubramani Vivekanandan
2024-04-03 11:22 ` [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection Balasubramani Vivekanandan
2024-04-03 11:57 ` Jani Nikula
2024-04-03 18:02 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Balasubramani Vivekanandan
2024-04-03 21:20 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic Balasubramani Vivekanandan
2024-04-08 13:00 ` Bhadane, Dnyaneshwar
2024-04-03 11:22 ` [PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Balasubramani Vivekanandan
2024-04-08 3:22 ` Chauhan, Shekhar
2024-04-03 11:22 ` [PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once() Balasubramani Vivekanandan
2024-04-03 12:07 ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 23/25] drm/xe/device: implement transient flush Balasubramani Vivekanandan
2024-04-03 12:13 ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 24/25] drm/i915/display: perform " Balasubramani Vivekanandan
2024-04-03 12:15 ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 25/25] drm/xe/bmg: Enable the display support Balasubramani Vivekanandan
2024-04-08 3:16 ` Chauhan, Shekhar
2024-04-08 6:23 ` Vivekanandan, Balasubramani
2024-04-03 11:29 ` ✓ CI.Patch_applied: success for Enable dislay support for Battlemage (rev2) Patchwork
2024-04-03 11:30 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-03 11:31 ` ✓ CI.KUnit: success " Patchwork
2024-04-03 11:42 ` ✓ CI.Build: " Patchwork
2024-04-03 11:50 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2024-04-03 11:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-03 11:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-03 12:00 ` ✓ CI.Hooks: " Patchwork
2024-04-03 12:01 ` ✗ CI.checksparse: warning " Patchwork
2024-04-04 3:58 ` ✗ Fi.CI.IGT: failure " Patchwork
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