All of lore.kernel.org
 help / color / mirror / Atom feed
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Subject: [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic
Date: Wed,  3 Apr 2024 16:52:48 +0530	[thread overview]
Message-ID: <20240403112253.1432390-21-balasubramani.vivekanandan@intel.com> (raw)
In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com>

From: Matt Roper <matthew.d.roper@intel.com>

Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index 3cad6dac06b0..542eea50093c 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 	if (DISPLAY_VER(dev_priv) >= 20) {
 		dev_priv->pch_type = PCH_LNL;
 		return;
-	} else if (IS_METEORLAKE(dev_priv)) {
+	} else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) {
 		/*
 		 * Both north display and south display are on the SoC die.
-		 * The real PCH is uninvolved in display.
+		 * The real PCH (if it even exists) is uninvolved in display.
 		 */
 		dev_priv->pch_type = PCH_MTL;
 		return;
-- 
2.25.1


  parent reply	other threads:[~2024-04-03 11:23 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-03 11:22 [PATCH v2 00/25] Enable dislay support for Battlemage Balasubramani Vivekanandan
2024-04-03 11:22 ` [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address Balasubramani Vivekanandan
2024-04-03 11:40   ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition Balasubramani Vivekanandan
2024-04-03 13:16   ` Lucas De Marchi
2024-04-03 11:22 ` [PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro Balasubramani Vivekanandan
2024-04-03 18:05   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 04/25] drm/i915/bmg: " Balasubramani Vivekanandan
2024-04-03 18:11   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms Balasubramani Vivekanandan
2024-04-03 19:02   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table Balasubramani Vivekanandan
2024-04-03 19:05   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Balasubramani Vivekanandan
2024-04-03 19:14   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future Balasubramani Vivekanandan
2024-04-03 19:15   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A Balasubramani Vivekanandan
2024-04-03 19:28   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address Balasubramani Vivekanandan
2024-04-03 12:00   ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration Balasubramani Vivekanandan
2024-04-03 20:11   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec Balasubramani Vivekanandan
2024-04-03 20:41   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 13/25] drm/i915/xe2hpd: Add display info Balasubramani Vivekanandan
2024-04-03 21:12   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming Balasubramani Vivekanandan
2024-04-03 21:00   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes Balasubramani Vivekanandan
2024-04-03 11:52   ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR Balasubramani Vivekanandan
2024-04-03 11:53   ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm Balasubramani Vivekanandan
2024-04-03 11:22 ` [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection Balasubramani Vivekanandan
2024-04-03 11:57   ` Jani Nikula
2024-04-03 18:02   ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Balasubramani Vivekanandan
2024-04-03 21:20   ` Matt Roper
2024-04-03 11:22 ` Balasubramani Vivekanandan [this message]
2024-04-08 13:00   ` [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic Bhadane, Dnyaneshwar
2024-04-03 11:22 ` [PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Balasubramani Vivekanandan
2024-04-08  3:22   ` Chauhan, Shekhar
2024-04-03 11:22 ` [PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once() Balasubramani Vivekanandan
2024-04-03 12:07   ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 23/25] drm/xe/device: implement transient flush Balasubramani Vivekanandan
2024-04-03 12:13   ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 24/25] drm/i915/display: perform " Balasubramani Vivekanandan
2024-04-03 12:15   ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 25/25] drm/xe/bmg: Enable the display support Balasubramani Vivekanandan
2024-04-08  3:16   ` Chauhan, Shekhar
2024-04-08  6:23     ` Vivekanandan, Balasubramani
2024-04-03 11:29 ` ✓ CI.Patch_applied: success for Enable dislay support for Battlemage (rev2) Patchwork
2024-04-03 11:30 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-03 11:31 ` ✓ CI.KUnit: success " Patchwork
2024-04-03 11:42 ` ✓ CI.Build: " Patchwork
2024-04-03 11:50 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2024-04-03 11:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-03 11:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-03 12:00 ` ✓ CI.Hooks: " Patchwork
2024-04-03 12:01 ` ✗ CI.checksparse: warning " Patchwork
2024-04-04  3:58 ` ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240403112253.1432390-21-balasubramani.vivekanandan@intel.com \
    --to=balasubramani.vivekanandan@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=matthew.d.roper@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.