From: "Christoph Müllner" <christoph.muellner@vrull.eu> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, "Björn Töpel" <bjorn@kernel.org>, "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>, "Heiko Stuebner" <heiko@sntech.de>, "Cooper Qu" <cooper.qu@linux.alibaba.com>, "Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>, "Huang Tao" <eric.huang@linux.alibaba.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Andrew Jones" <ajones@ventanamicro.com>, "Conor Dooley" <conor@kernel.org>, "Qingfang Deng" <dqfext@gmail.com>, "Alexandre Ghiti" <alex@ghiti.fr>, "Samuel Holland" <samuel.holland@sifive.com> Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>, "Conor Dooley" <conor.dooley@microchip.com> Subject: [PATCH v3 2/2] riscv: T-Head: Test availability bit before enabling MAE errata Date: Sun, 7 Apr 2024 23:32:36 +0200 [thread overview] Message-ID: <20240407213236.2121592-3-christoph.muellner@vrull.eu> (raw) In-Reply-To: <20240407213236.2121592-1-christoph.muellner@vrull.eu> T-Head's memory attribute extension (XTheadMae) (non-compatible equivalent of RVI's Svpbmt) is currently assumed for all T-Head harts. However, QEMU recently decided to drop acceptance of guests that write reserved bits in PTEs. As XTheadMae uses reserved bits in PTEs and Linux applies the MAE errata for all T-Head harts, this broke the Linux startup on QEMU emulations of the C906 emulation. This patch attempts to address this issue by testing the MAE-enable bit in the th.sxstatus CSR. This CSR is available in HW and can be emulated in QEMU. This patch also makes the XTheadMae probing mechanism reliable, because a test for the right combination of mvendorid, marchid, and mimpid is not sufficient to enable MAE. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- arch/riscv/errata/thead/errata.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 6e7ee1f16bee..bf6a0a6318ee 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,6 +19,9 @@ #include <asm/patch.h> #include <asm/vendorid_list.h> +#define CSR_TH_SXSTATUS 0x5c0 +#define SXSTATUS_MAEE _AC(0x200000, UL) + static bool errata_probe_mae(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -28,11 +31,14 @@ static bool errata_probe_mae(unsigned int stage, if (arch_id != 0 || impid != 0) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || - stage == RISCV_ALTERNATIVES_MODULE) - return true; + if (stage != RISCV_ALTERNATIVES_EARLY_BOOT && + stage != RISCV_ALTERNATIVES_MODULE) + return false; - return false; + if (!(csr_read(CSR_TH_SXSTATUS) & SXSTATUS_MAEE)) + return false; + + return true; } /* -- 2.44.0
WARNING: multiple messages have this Message-ID (diff)
From: "Christoph Müllner" <christoph.muellner@vrull.eu> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, "Björn Töpel" <bjorn@kernel.org>, "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>, "Heiko Stuebner" <heiko@sntech.de>, "Cooper Qu" <cooper.qu@linux.alibaba.com>, "Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>, "Huang Tao" <eric.huang@linux.alibaba.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Andrew Jones" <ajones@ventanamicro.com>, "Conor Dooley" <conor@kernel.org>, "Qingfang Deng" <dqfext@gmail.com>, "Alexandre Ghiti" <alex@ghiti.fr>, "Samuel Holland" <samuel.holland@sifive.com> Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>, "Conor Dooley" <conor.dooley@microchip.com> Subject: [PATCH v3 2/2] riscv: T-Head: Test availability bit before enabling MAE errata Date: Sun, 7 Apr 2024 23:32:36 +0200 [thread overview] Message-ID: <20240407213236.2121592-3-christoph.muellner@vrull.eu> (raw) In-Reply-To: <20240407213236.2121592-1-christoph.muellner@vrull.eu> T-Head's memory attribute extension (XTheadMae) (non-compatible equivalent of RVI's Svpbmt) is currently assumed for all T-Head harts. However, QEMU recently decided to drop acceptance of guests that write reserved bits in PTEs. As XTheadMae uses reserved bits in PTEs and Linux applies the MAE errata for all T-Head harts, this broke the Linux startup on QEMU emulations of the C906 emulation. This patch attempts to address this issue by testing the MAE-enable bit in the th.sxstatus CSR. This CSR is available in HW and can be emulated in QEMU. This patch also makes the XTheadMae probing mechanism reliable, because a test for the right combination of mvendorid, marchid, and mimpid is not sufficient to enable MAE. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- arch/riscv/errata/thead/errata.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 6e7ee1f16bee..bf6a0a6318ee 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,6 +19,9 @@ #include <asm/patch.h> #include <asm/vendorid_list.h> +#define CSR_TH_SXSTATUS 0x5c0 +#define SXSTATUS_MAEE _AC(0x200000, UL) + static bool errata_probe_mae(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -28,11 +31,14 @@ static bool errata_probe_mae(unsigned int stage, if (arch_id != 0 || impid != 0) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || - stage == RISCV_ALTERNATIVES_MODULE) - return true; + if (stage != RISCV_ALTERNATIVES_EARLY_BOOT && + stage != RISCV_ALTERNATIVES_MODULE) + return false; - return false; + if (!(csr_read(CSR_TH_SXSTATUS) & SXSTATUS_MAEE)) + return false; + + return true; } /* -- 2.44.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-07 21:32 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-07 21:32 [PATCH v3 0/2] RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE Christoph Müllner 2024-04-07 21:32 ` Christoph Müllner 2024-04-07 21:32 ` [PATCH v3 1/2] riscv: thead: Rename T-Head PBMT to MAE Christoph Müllner 2024-04-07 21:32 ` Christoph Müllner 2024-04-07 21:32 ` Christoph Müllner [this message] 2024-04-07 21:32 ` [PATCH v3 2/2] riscv: T-Head: Test availability bit before enabling MAE errata Christoph Müllner 2024-04-08 1:58 ` Yangyu Chen 2024-04-08 1:58 ` Yangyu Chen 2024-04-08 6:00 ` Christoph Müllner 2024-04-08 6:00 ` Christoph Müllner 2024-04-08 7:36 ` Yangyu Chen 2024-04-08 7:36 ` Yangyu Chen 2024-04-08 7:55 ` Christoph Müllner 2024-04-08 7:55 ` Christoph Müllner 2024-04-08 8:10 ` Conor Dooley 2024-04-08 8:10 ` Conor Dooley 2024-04-08 8:21 ` Yangyu Chen 2024-04-08 8:21 ` Yangyu Chen 2024-04-08 9:06 ` Conor Dooley 2024-04-08 9:06 ` Conor Dooley 2024-04-25 23:00 ` [PATCH v3 0/2] RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE patchwork-bot+linux-riscv 2024-04-25 23:00 ` patchwork-bot+linux-riscv
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20240407213236.2121592-3-christoph.muellner@vrull.eu \ --to=christoph.muellner@vrull.eu \ --cc=ajones@ventanamicro.com \ --cc=alex@ghiti.fr \ --cc=alistair.francis@wdc.com \ --cc=aou@eecs.berkeley.edu \ --cc=bjorn@kernel.org \ --cc=conor.dooley@microchip.com \ --cc=conor@kernel.org \ --cc=cooper.qu@linux.alibaba.com \ --cc=dbarboza@ventanamicro.com \ --cc=dqfext@gmail.com \ --cc=eric.huang@linux.alibaba.com \ --cc=heiko@sntech.de \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=philipp.tomsich@vrull.eu \ --cc=samuel.holland@sifive.com \ --cc=zhiwei_liu@linux.alibaba.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.